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W97AH6KB / w97ah2kb lpddr2 - s4b 1gb publication release date: may 15, 2014 revision: a01 - 001 - 1 - table of contents - 1. general description ................................ ................................ ................................ ................................ ............ 6 2. features ................................ ................................ ................................ ................................ ................................ .... 6 3. order information ................................ ................................ ................................ ................................ ................ 7 4. pin configuration ................................ ................................ ................................ ................................ .................. 8 4.1 134 ball vfbga ................................ ................................ ................................ ................................ ............................. 8 4.2 168 ball wfbga ................................ ................................ ................................ ................................ ............................ 9 5. pin description ................................ ................................ ................................ ................................ ..................... 10 5.1 basic functionality ................................ ................................ ................................ ................................ ....................... 10 5.2 addressing table ................................ ................................ ................................ ................................ ......................... 11 6. block diagram ................................ ................................ ................................ ................................ ....................... 12 7. functional de scription ................................ ................................ ................................ ................................ ..... 13 7.1 simplified lpddr2 state diagram ................................ ................................ ................................ .............................. 13 7.1.1 simplified lpddr2 bus interface state diagram ................................ ................................ ................................ ......... 14 7.2 power - up, initialization, and power - off ................................ ................................ ................................ ........................ 15 7.2.1 power ramp and device initialization ................................ ................................ ................................ .......................... 15 7.2.2 timing parameters for initialization ................................ ................................ ................................ .............................. 17 7.2.3 power ramp and initialization sequence ................................ ................................ ................................ .................... 17 7.2.4 initialization after reset (without power ramp) ................................ ................................ ................................ ............. 18 7.2.5 power - off sequence ................................ ................................ ................................ ................................ .................... 18 7.2.6 ti ming parameters power - off ................................ ................................ ................................ ................................ ..... 18 7.2.7 uncontrolled power - off sequence ................................ ................................ ................................ .............................. 18 7.3 mode register definition ................................ ................................ ................................ ................................ .............. 19 7.3. 1 mode register assignment and definition ................................ ................................ ................................ ................... 19 7.3.1.1 mode register assignment ................................ ................................ ................................ ............................... 19 7.3.2 mr0_device information (ma[7:0] = 00h) ................................ ................................ ................................ ................... 20 7.3.3 mr1_device feature 1 (ma[7:0] = 01h) ................................ ................................ ................................ ...................... 20 7.3.3.1 burst sequence by burst length (bl), burst type (bt), and warp control (wc) ................................ .............. 21 7.3.3.2 non wrap restrictions ................................ ................................ ................................ ................................ ...... 21 7. 3.4 mr2_device feature 2 (ma[7:0] = 02h) ................................ ................................ ................................ ...................... 22 7.3.5 mr3_i/o configuration 1 (ma[7:0] = 03h) ................................ ................................ ................................ ................... 22 7.3.6 mr4_device temperature (ma[7:0] = 04h) ................................ ................................ ................................ ................. 22 7.3.7 mr5_basic configuration 1 (ma[7:0] = 05h) ................................ ................................ ................................ ............... 23 7.3.8 mr6_basic configuration 2 (ma[7:0] = 06h) ................................ ................................ ................................ ............... 23 7.3.9 mr7_basic configuration 3 (ma[7:0] = 07h) ................................ ................................ ................................ ............... 23 7.3.10 mr8_basic configuration 4 (ma[7:0] = 08h) ................................ ................................ ................................ ............... 23 7.3.11 mr9_test mode (ma[7:0] = 09h) ................................ ................................ ................................ ................................ 23 7.3.12 mr10_calibration (ma[7:0] = 0ah) ................................ ................................ ................................ ............................. 24 7.3.13 mr16_pasr_bank mask (ma[7:0] = 10h) ................................ ................................ ................................ .................. 24 7.3.14 mr17_pasr_segment mask (ma[7:0] = 11h) ................................ ................................ ................................ ............ 25 7.3.15 mr32_dq calibration pattern a (ma[7:0] = 20h) ................................ ................................ ................................ ........ 25 7.3.16 mr40_dq calibration pattern b (ma[7:0] = 28h) ................................ ................................ ................................ ........ 25 7.3.17 mr63_reset (ma[7:0] = 3fh): mrw only ................................ ................................ ................................ ................... 25 7.4 command definitions and timing diagrams ................................ ................................ ................................ ................ 26 7.4.1 activate command ................................ ................................ ................................ ................................ ...................... 26 7.4.1.1 ac tivate command cycle: trcd = 3, trp = 3, trrd = 2 ................................ ................................ ................... 26 7.4.1.2 tfaw timing ................................ ................................ ................................ ................................ ..................... 27 7.4.1.3 command input setup and hold timing ................................ ................................ ................................ ............ 27 7.4.1.4 cke input setup and hold timing ................................ ................................ ................................ .................... 28 7.4.2 read and write access modes ................................ ................................ ................................ ................................ .... 28 7.4.3 burst read command ................................ ................................ ................................ ................................ ................. 28 7.4.3.1 data output (read) timing (tdqsckmax) ................................ ................................ ................................ ........ 29 7.4.3.2 data output (read) timing (tdqsckmin) ................................ ................................ ................................ ......... 30
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 2 - 7.4.3.3 burst read: rl = 5, bl = 4, tdqsck > tck ................................ ................................ ................................ ...... 30 7.4.3.4 burst read: rl = 3, bl = 8, tdqsck < tck ................................ ................................ ................................ ...... 31 7.4.3.5 lpddr2: tdqsckdl timing ................................ ................................ ................................ ............................ 31 7.4.3.6 lpddr2: tdqsckdm timing ................................ ................................ ................................ ........................... 32 7.4.3.7 lpddr2: tdqsckds timing ................................ ................................ ................................ ............................ 32 7.4.3.8 burst read followed by burst write: rl = 3, wl = 1, bl = 4 ................................ ................................ ............ 33 7.4.3.9 seamless burst read: rl = 3, bl= 4, tccd = 2 ................................ ................................ ............................... 33 7.4.4 reads interrupted by a read ................................ ................................ ................................ ................................ ....... 34 7.4.4.1 read burst interrupt example: rl = 3, bl= 8, tccd = 2 ................................ ................................ ................... 34 7.4.5 burst write operation ................................ ................................ ................................ ................................ .................. 34 7.4.5.1 data input (write) timing ................................ ................................ ................................ ................................ .. 35 7.4.5.2 burst write: wl = 1, bl= 4 ................................ ................................ ................................ ............................... 35 7.4.5.3 burst wirte followed by burst read: rl = 3, wl= 1, bl= 4 ................................ ................................ .............. 36 7.4.5.4 seamless burst write: wl= 1, bl = 4, tccd = 2 ................................ ................................ ............................... 36 7.4.6 writes interrupted by a write ................................ ................................ ................................ ................................ ....... 37 7.4.6.1 write burst interrupt timing: wl = 1, bl = 8, tccd = 2 ................................ ................................ .................... 37 7.4.7 burst terminate ................................ ................................ ................................ ................................ ........................... 37 7.4.7.1 burst write truncated by bst: wl = 1, bl = 16 ................................ ................................ ............................... 38 7.4.7.2 burst read truncated by bst: rl = 3, bl = 16 ................................ ................................ ................................ 38 7.4.8 write data mask ................................ ................................ ................................ ................................ .......................... 39 7.4.8.1 write data mask timing ................................ ................................ ................................ ................................ .... 39 7.4.9 precharge operation ................................ ................................ ................................ ................................ ................... 40 7.4.9. 1 bank selection for precharge by address bits ................................ ................................ ................................ .. 40 7.4.10 burst read operation followed by precharge ................................ ................................ ................................ ............. 40 7.4.10.1 burst read followed by precharge: rl = 3, bl = 8, ru(trtp(min)/tck) = 2 ................................ .................... 41 7.4.10.2 burst read followed by precharge: rl = 3, bl = 4, ru(trtp(min)/tck) = 3 ................................ .................... 41 7.4.11 burst write followed by precharge ................................ ................................ ................................ ............................. 42 7.4.11.1 burst write follwed by precharge: wl = 1, bl = 4 ................................ ................................ ............................ 42 7.4.12 auto precharge operation ................................ ................................ ................................ ................................ ........... 43 7.4.13 burst read with auto - precharge ................................ ................................ ................................ ................................ . 43 7.4.13.1 burst read with auto - precharge: rl = 3, bl = 4, ru(tr tp(min)/tck) = 2 ................................ ........................ 43 7.4.14 burst write with auto - precharge ................................ ................................ ................................ ................................ .. 44 7.4.14.1 burst write with auto - precharge: wl = 1, bl = 4 ................................ ................................ .............................. 44 7.4.14.2 precharge & auto precharge clarification ................................ ................................ ................................ ......... 45 7.4.15 refresh command ................................ ................................ ................................ ................................ ...................... 46 7.4.15.1 command scheduling separations related to refresh ................................ ................................ ..................... 47 7.4.16 lpddr2 sdram refresh requirements ................................ ................................ ................................ .................... 47 7.4.16.1 definition of tsrf ................................ ................................ ................................ ................................ .............. 48 7.4.16.2 regular, distributed refresh pattern ................................ ................................ ................................ ................. 50 7.4.16.3 allowable transition from repetitive burst refresh ................................ ................................ ........................... 50 7.4.16.4 not - allowable transition from repetitive burst refresh ................................ ................................ .................. 51 7.4.16.5 recommended self - refresh entry and exit ................................ ................................ ................................ ...... 51 7.4.16.6 all bank refresh operation ................................ ................................ ................................ ............................... 52 7.4.16.7 per bank refresh operation ................................ ................................ ................................ ............................. 52 7.4.17 self refresh operation ................................ ................................ ................................ ................................ ................ 53 7.4.18 partial array self - refresh: bank masking ................................ ................................ ................................ .................... 54 7.4.19 partial array self - refresh: segment masking ................................ ................................ ................................ .............. 54 7.4.20 mode register read command ................................ ................................ ................................ ................................ .. 55 7.4.20.1 mode register read timing example: rl = 3, tmrr = 2 ................................ ................................ .................. 56 7.4.20.2 read to mrr timing example: rl = 3, tmrr = 2 ................................ ................................ ............................ 57 7.4.20.3 burst write followed by mrr: rl = 3, wl = 1, bl = 4 ................................ ................................ ..................... 57 7.4.21 tempera ture sensor ................................ ................................ ................................ ................................ .................... 58 7.4.21.1 temperature sensor timing ................................ ................................ ................................ ............................. 59 7.4.21.2 dq calibration ................................ ................................ ................................ ................................ .................. 59 7.4.21.3 mr32 and mr40 dq calibration timing example: rl = 3, tmrr = 2 ................................ ............................... 60 7.4.22 mode register write command ................................ ................................ ................................ ................................ ... 61
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 3 - 7.4.22.1 mode register write timing example: rl = 3, tmrw = 5 ................................ ................................ ................. 61 7.4.22.2 truth table for mode register read (mrr) and mode register write (mrw) ................................ .................. 61 7.4.23 mode register write reset (mrw reset) ................................ ................................ ................................ ................... 62 7.4.24 mode register write zq calibration command ................................ ................................ ................................ ........... 62 7.4.24.1 zq calibration initialization timing example ................................ ................................ ................................ ..... 63 7.4.24.2 zq calibration short timing example ................................ ................................ ................................ ............... 63 7.4.24.3 zq calibration long timing example ................................ ................................ ................................ ................ 64 7.4.24.4 zq calibration reset timing example ................................ ................................ ................................ .............. 64 7.4.24.5 zq external resistor value, tolerance, and capacitive loading ................................ ................................ ...... 65 7.4.25 power - down ................................ ................................ ................................ ................................ ................................ 65 7.4.25.1 basic power down entry and exit timing ................................ ................................ ................................ ......... 65 7.4.25.2 cke intensive environment ................................ ................................ ................................ .............................. 66 7.4.25.3 refresh to refresh timing with cke intensive environment ................................ ................................ ............. 66 7.4.25.4 read to power - down entry ................................ ................................ ................................ ............................... 67 7.4.25.5 read with auto precharge to power - down entry ................................ ................................ .............................. 67 7.4.25.6 write to power - down entry ................................ ................................ ................................ ............................... 68 7.4.25.7 write with auto precharge to power - down entry ................................ ................................ .............................. 68 7.4.25.8 refresh command to power - down entry ................................ ................................ ................................ .......... 69 7.4.25.9 activate command to power - down entry ................................ ................................ ................................ ......... 69 7.4.25.10 precharge/precharge - all command to power - down entry ................................ ................................ ............... 69 7.4.25.11 mode register read to power - down entry ................................ ................................ ................................ ....... 70 7.4.25.12 mrw command to power - down entry ................................ ................................ ................................ ............. 70 7.4.26 deep power - down ................................ ................................ ................................ ................................ ...................... 70 7.4.26.1 deep power down entry and exit timing ................................ ................................ ................................ .......... 71 7.4.27 input clock stop and frequency change ................................ ................................ ................................ .................... 71 7.4.28 no operation command ................................ ................................ ................................ ................................ .............. 72 7.5 truth tables ................................ ................................ ................................ ................................ ................................ . 72 7.5.1 command truth table ................................ ................................ ................................ ................................ ................. 73 7.5.2 cke truth table ................................ ................................ ................................ ................................ .......................... 74 7.5.3 current state bank n - command to bank n truth table ................................ ................................ ............................. 75 7.5.4 current state bank n - command to bank m truth table ................................ ................................ ............................ 77 7.5.5 data mask truth table ................................ ................................ ................................ ................................ ................ 78 8. electrical characteristic ................................ ................................ ................................ .............................. 79 8.1 absolute maximum dc ratings ................................ ................................ ................................ ................................ ... 79 8.2 ac & dc operating conditions ................................ ................................ ................................ ................................ .... 79 8.2.1 recommended dc operating conditions ................................ ................................ ................................ .................... 79 8.2.1.1 recommended dc operating conditions ................................ ................................ ................................ ......... 79 8.2.2 input leakage current ................................ ................................ ................................ ................................ ................. 80 8.2. 3 operating temperature conditions ................................ ................................ ................................ .............................. 80 8.2.4 ac and dc input measurement levels ................................ ................................ ................................ ........................ 80 8.2.4.1 ac and dc logic input levels for single - ended signals ................................ ................................ ................... 80 8.2.4.1.1 single - ended ac and dc input levels for ca and cs_n inputs ................................ ................................ ....... 80 8.2.4.1.2 single - ended ac and dc input levels for cke ................................ ................................ ................................ 81 8.2.4.1.3 single - ended ac and dc input levels for dq and dm ................................ ................................ ..................... 81 8.2.4.2 vref tolerances ................................ ................................ ................................ ................................ ................ 81 8.2.4.2.1 vref(dc) tolerance and vref ac - noise limits ................................ ................................ ................................ 82 8.2.4.3 input signal ................................ ................................ ................................ ................................ ....................... 83 8.2.4.3.1 lpddr2 - 800/1066 input signal ................................ ................................ ................................ ........................ 83 8.2.4.4 ac and dc logic input levels for differential signals ................................ ................................ ....................... 84 8.2.4.4.1 differential signal definition ................................ ................................ ................................ .............................. 84 8.2.4.4.2 differential swing requirements for clock (ck_t - ck_c) and strobe (dqs_t - dqs_c) ................................ ...... 84 8.2.4.5 single - ended requirements for differential signals ................................ ................................ .......................... 85 8.2.4.6 differential input cross point voltage ................................ ................................ ................................ ................ 86 8.2.4.7 slew rate definitions for single - ended input signals ................................ ................................ ....................... 87 8.2.4.8 slew rate definitions for differential input signals ................................ ................................ ............................ 87
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 4 - 8.2.5 ac and dc output measurement levels ................................ ................................ ................................ ..................... 88 8.2.5.1 single ended ac and dc output levels ................................ ................................ ................................ ........... 88 8.2.5.2 differential ac and dc output levels ................................ ................................ ................................ ............... 88 8.2.5.3 single ended output slew rate ................................ ................................ ................................ ........................ 88 8.2.5.4 differential output slew rate ................................ ................................ ................................ ............................ 90 8.2.5.5 overshoot and undershoot specifications ................................ ................................ ................................ ........ 91 8.2.6 output buffer characteristics ................................ ................................ ................................ ................................ ....... 92 8.2.6.1 hsul_12 driver output timing referen ce load ................................ ................................ ............................... 92 8.2.6.2 ron pu and ron pd resistor definition ................................ ................................ ................................ .............. 92 8.2.6.3 ron pu and ron pd characteristics with zq calibration ................................ ................................ ..................... 93 8.2.6.4 output driver temperature and voltage sensitivity ................................ ................................ ........................... 93 8.2.6.5 ron pu and ron pd characteristics without zq calibration ................................ ................................ ................ 94 8.2.6.6 rzq i - v curve ................................ ................................ ................................ ................................ .................. 95 8.2.6.7 input/output capacitance ................................ ................................ ................................ ................................ . 97 8.3 idd specification parameters and test conditions ................................ ................................ ................................ ..... 98 8.3.1 idd measurement conditions ................................ ................................ ................................ ................................ ...... 98 8.3.1.1 definition of switching for ca input signals ................................ ................................ ................................ ...... 98 8.3.1.2 definition of switching for idd4r ................................ ................................ ................................ ...................... 99 8.3.1.3 definition of switching for idd4w ................................ ................................ ................................ ..................... 99 8.3.2 idd specifications ................................ ................................ ................................ ................................ ..................... 100 8.3.2.1 lpddr2 idd specification parameters and operating conditions, - 40c~85c (x16, x32) ............................ 100 8.3.2.2 idd6 partial array self - refresh current, - 40c~85c (x16, x32) ................................ ................................ .... 102 8.4 clock specification ................................ ................................ ................................ ................................ ..................... 102 8.4.1 definition for tck(avg) and nck ................................ ................................ ................................ ................................ . 102 8.4.2 definition for tck(abs) ................................ ................................ ................................ ................................ ............... 102 8.4.3 definition for tch(avg) and tcl(avg) ................................ ................................ ................................ .......................... 103 8.4.4 definition for tjit(per) ................................ ................................ ................................ ................................ ................ 103 8.4.5 definition for tjit(cc) ................................ ................................ ................................ ................................ ................. 103 8.4.6 definition for terr(nper) ................................ ................................ ................................ ................................ ........... 103 8.4.7 definition for duty dycle jitter tjit(duty) ................................ ................................ ................................ .................... 104 8.4.8 definition for tck(abs), tch(abs) and tcl(abs) ................................ ................................ ................................ .......... 104 8.5 period clock jitter ................................ ................................ ................................ ................................ ...................... 104 8.5.1 clock period jitter effects on core timing parameters ................................ ................................ ............................. 104 8.5.1.1 cycle time de - rating for core timing parameters ................................ ................................ .......................... 104 8.5.1.2 clock cycle de - rating for core tim ing parameters ................................ ................................ ......................... 105 8.5.2 clock jitter effects on command/address timing parameters ................................ ................................ .................. 105 8.5.3 clock jitter effects on read ttiming parameters ................................ ................................ ................................ ....... 105 8.5.3.1 trpre ................................ ................................ ................................ ................................ ............................ 105 8.5.3.2 tlz(dq), t hz(dq), tdqsck, tlz(dqs), thz(dqs) ................................ ................................ ......................... 105 8.5.3.3 tqsh, tqsl ................................ ................................ ................................ ................................ ..................... 105 8.5.3.4 trpst ................................ ................................ ................................ ................................ ............................. 106 8.5.4 clock jitter effects on write timing parameters ................................ ................................ ................................ ........ 106 8.5.4.1 tds, tdh ................................ ................................ ................................ ................................ ......................... 106 8.5.4.2 tdss, tdsh ................................ ................................ ................................ ................................ ..................... 106 8.5.4.3 tdqs s ................................ ................................ ................................ ................................ ............................ 106 8.6 refresh requirements ................................ ................................ ................................ ................................ ............... 107 8.6.1 refresh requirement parameters ................................ ................................ ................................ ............................. 107 8.7 ac timings ................................ ................................ ................................ ................................ ................................ 108 8.7.1 lpddr2 ac timing ................................ ................................ ................................ ................................ .................. 108 8.7.2 ca and cs_n setup, hold and derating ................................ ................................ ................................ .................... 113 8.7.2.1 ca and cs_n setup and hold base - values for 1v/ns ................................ ................................ .................... 113 8.7.2.2 derating values lpddr2 tis/tih - ac/dc based ac220 ................................ ................................ ................ 114 8.7.2.3 required time tvac above vih(ac) {below vil(ac)} for valid transition ................................ ......................... 114 8.7.2.4 nominal slew rate and tvac for setup time tis for ca and cs_n with respect to cloc k .............................. 115 8.7.2.5 nominal slew rate for hold time tih for ca and cs_n with respect to clock ................................ ................ 116
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 5 - 8.7.2.6 tangent line for setup time tis for ca and cs_n with respect to clock ................................ ....................... 117 8.7.2.7 tangent line for hold time tih for ca and cs_n with respect to clock ................................ ......................... 118 8.7.3 data setup, hold and slew rate derating ................................ ................................ ................................ ................. 119 8.7.3.1 data setup and hold base - values ................................ ................................ ................................ .................. 119 8.7.3.2 derating values lpddr2 tds/tdh - ac/dc based ac220 ................................ ................................ ............. 120 8.7.3.3 required time tvac above vih(ac) {below vil(ac)} for valid transition ................................ ......................... 120 8.7.3.4 nominal slew rate and tvac for setup time tds for dq with respect to strobe ................................ ........... 121 8.7.3.5 nominal slew rate for hold time tdh for dq with respect to strobe ................................ .............................. 122 8.7.3.6 tangent line for setup time tds for dq with respect to strobe ................................ ................................ .... 123 8.7.3.7 tangent line for hold time tdh for dq with respect to strobe ................................ ................................ ...... 124 9. package dimensions ................................ ................................ ................................ ................................ .......... 125 10. revision history ................................ ................................ ................................ ................................ ................. 127
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 6 - 1. general description lpddr2 is a high - speed sdram device internally configured as a n 8 - bank memory. the se device s contains 1 gb has 1,073,741,824 bits . all lpddr2 devices use a double data rate archi t ecture on the command/address (ca) bus to reduce the number of input pin s in the system. the 10 - bit ca bus contains command, address, and bank/row buffer information. each command uses one clock cycle, during which command information is transferred on bot h the positive and negative edge of the clock . for lpddr2 devices, accesses begin with the registration of an activate command, which is then followed by a read or write command. the address and ba bits registered coincident with the activate command are used to select the row and the bank to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access . 2. features ? v dd 1 = 1. 7~1.95 v ? v dd 2 /v ddca /v ddq = 1.14v~ 1.30v ? data width: x16 / x32 ? clock rate: up to 533 mhz ? data rate: up to 1066 mb / s / pin ? four - bit prefetch ddr architecture ? eight internal banks for concurrent operation ? programmable read and write latencies ( rl/wl) ? programmable burst lengths: 4, 8, or 16 ? per bank refresh ? partial array self - refresh(pasr) ? deep power down mode (dpd mode) ? programmable output buffer driver strength ? data mask (dm) for write data ? clock stop capability during idle periods ? double data rate for data output ? differential clock inputs ? bidirec tional differential data strobe ? interface: hsul_12 ? jedec lpddr2 - s4b compliance ? support p ac kage: s ingle channel: 1 34 v fbga (1 0 mm x 11.5 mm ) s ingle channel: 168 wfbga (12 mm x12 mm ) ? operating temperature range: - 25 c t case 8 5c - 40 c t case 8 5c
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 7 - 3. order information part number vdd1/vdd2/vddq i/o width package others w97ah2kbqx2i 1.8v/1.2v/1.2v 32 168wfbga 400m h z, - 40c ~ 8 5c w97ah2kbqx2e 1.8v/1.2v/1.2v 32 168wfbga 400m h z, - 25 c ~ 8 5c W97AH6KBqx2i 1.8v/1.2v/1.2v 16 168wfbga 400m h z, - 40c ~ 8 5c W97AH6KBqx2e 1.8v/1.2v/1.2v 16 168wfbga 400m h z, - 25 c ~ 8 5c w97ah2kbqx 1 i 1.8v/1.2v/1.2v 32 168wfbga 533 m h z, - 40c ~ 8 5c w97ah2kbqx 1 e 1.8v/1.2v/1.2v 32 168wfbga 533 m h z, - 25 c ~ 8 5c W97AH6KBqx 1 i 1.8v/1.2v/1.2v 16 168wfbga 533 m h z, - 40c ~ 8 5c W97AH6KBqx 1 e 1.8v/1.2v/1.2v 16 168wfbga 533 m h z, - 25 c ~ 8 5c w97ah2kb v x2i 1.8v/1.2v/1.2v 32 134vfbga 400m h z, - 40c ~ 8 5c w97ah2kb v x2e 1.8v/1.2v/1.2v 32 134vfbga 400m h z, - 25 c ~ 8 5c W97AH6KB v x2i 1.8v/1.2v/1.2v 16 134vfbga 400m h z, - 40c ~ 8 5c W97AH6KB v x2e 1.8v/1.2v/1.2v 16 134vfbga 400m h z, - 25 c ~ 8 5c w97ah2kb v x 1 i 1.8v/1.2v/1.2v 32 134vfbga 533 m h z, - 40c ~ 8 5c w97ah2kb v x 1 e 1.8v/1.2v/1.2v 32 134vfbga 533 m h z, - 25 c ~ 8 5c W97AH6KB v x 1i 1.8v/1.2v/1.2v 16 134vfbga 533 m h z, - 40c ~ 8 5c W97AH6KB v x 1 e 1.8v/1.2v/1.2v 16 134vfbga 533 m h z, - 25 c ~ 8 5c
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 8 - 4. pin configuration 4.1 134 ball vfbga [top view] 1 2 3 4 5 6 7 8 9 10 a dnu dnu dnu dnu a b dnu nc nc vdd2 vdd1 dq31 nc dq29 nc dq26 nc dnu b c vdd1 vss nc vss vssq vddq dq25 nc vssq vddq c d vss vdd2 zq0 vddq dq30 nc dq27 nc dqs3_t nc dqs3_c nc vssq d 1st row 2nd row x32 device x16 device e vssca ca9 ca8 dq28 nc dq24 nc dm3 nc dq15 vddq vssq e f vddca ca6 ca7 vssq dq11 dq13 dq14 dq12 vddq f g vdd2 ca5 vref(ca) dqs1_c dqs1_t dq10 dq9 dq8 vssq g h vddca vss ck_c dm1 vddq h j vssca nc ck_t vssq vddq vdd2 vss vref(dq) j k cke0 nc nc dm0 vddq k l cs0_n nc nc dqs0_c dqs0_t dq5 dq6 dq7 vssq l lpddr2 dq m ca4 ca3 ca2 vssq dq4 dq2 dq1 dq3 vddq m lpddr2 ca n vssca vddca ca1 dq19 nc dq23 nc dm2 nc dq0 vddq vssq n power p vss vdd2 ca0 vddq dq17 nc dq20 nc dqs2_t nc dqs2_c nc vssq p ground r vdd1 vss nc vss vssq vddq dq22 nc vssq vddq r do not use /nc t dnu nc nc vdd2 vdd1 dq16 nc dq18 nc dq21 nc dnu t zq u dnu dnu dnu dnu u clock 1 2 3 4 5 6 7 8 9 10 b all definition where 2 labe's are present
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 9 - 4.2 1 68 ball w fbga 168ball wfbga [top view] note: x16: dq16~dq31, dm2,dm3,dqs2_t,dqs2_c, dqs3_t & dqs3_c is nc . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a nc nc nc nc nc nc nc nc nc nc vdd1 vssq dq30 dq29 vssq dq26 dq25 vssq dqs3_c vdd1 vss nc nc b nc nc vdd1 nc vss nc nc vss nc vss vdd2 dq31 vddq dq28 dq27 vddq dq24 dqs3_t vddq dm3 vdd2 nc nc c vss vdd2 dq15 vssq d nc nc vddq dq14 e nc nc dq12 dq13 f nc vss dq11 vssq g nc nc vddq dq10 h nc nc dq8 dq9 j nc vss dqs1_t vssq k nc nc vddq dqs1_c l nc nc vdd2 dm1 m nc vss vref(dq) vss n nc vdd1 vdd1 dm0 p zq vref(ca) dqs0_c vssq r vss vdd2 vddq dqs0_t t ca9 ca8 dq6 dq7 u ca7 vddca dq5 vssq v vssca ca6 vddq dq4 w ca5 vddca dq2 dq3 y ck_c ck_t dq1 vssq aa vss vdd2 vddq dq0 ab nc nc cs_n nc vdd1 ca1 vssca ca3 ca4 vdd2 vss dq16 vddq dq18 dq20 vddq dq22 dqs2_t vddq dm2 vdd2 nc nc ac nc nc cke nc vss ca0 ca2 vddca vss nc nc vssq dq17 dq19 vssq dq21 dq23 vssq dqs2_c vdd1 vss nc nc
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 10 - 5. p in description 5.1 basic functionality n am e ty pe d e sc r i p ti o n c k_t, ck_c i n pu t cl o ck : ck_ t a n d c k _ c are differenti al c l oc k i nputs . al l d oub l e data rate ( d dr ) c a i nputs are s a m p le d on b o t h po s itive a nd n egativ e edg e of c k _ t . s i ngl e data rate (sd r ) i nputs, c s_ n a n d cke, a r e s a m p le d a t t h e positive cl o ck e d ge. c l oc k is d e f i ne d as the di f f ere n t i al p a i r , c k_ t a nd ck_ c . t h e pos i t i v e c lock e dg e i s d ef i ne d by the crosspo i nt of a r i sing c k _ t and a fall i ng c k _ c. t he n e gative cl o ck ed g e is d ef i ne d b y the crosspo i n t of a f a lli n g c k _ t a nd a risin g c k_ c . c ke i n pu t cl o ck e n able: cke hig h act i vat e s and c k e l o w deactivates i n t e rnal cl o c k s i gn a ls and ther e f o r e d evic e in p ut b u ffer s an d o u t p ut dr i v er s . powe r savi n gs mo d es ar e e ntere d a n d e x i t e d th ro ug h c ke transitions. cke is consi d ered p a rt o f th e comman d c o de . see 7. 5 . 1 command truth table for command code descriptions. cke is sample d a t the pos i tiv e c l oc k e dg e . c s _n i n pu t chip select : cs _ n is consi d ered p art o f the c o mma n d cod e . see 7. 5 . 1 command truth table for command code descriptions. cs _ n i s s a m p led at t h e positive cl o ck e d ge. c a [n:0] i n pu t ddr command/address inputs: uni - directional command/address bus inputs. ca is conside r ed part of th e command code . see 7. 5 . 1 command truth table for command code descriptions. dq [n: 0 ] i /o dat a i n p ut s / o u t pu t : bi - d i r e ct i ona l d at a b us . n=15 for 16 bits dq; n=31 for 32 bits dq. dqs n _t, dqs n _c i /o data strobe (bi - directional, differential ): the data strobe is bi - directional (used for read and write data) and differential (dqs_t and dqs_c). it is output with read data and input with write data. dqs_t is edge - aligned to read data and centered with write data. for x16, dqs0_t and dqs0_c correspond to the data on dq0 - 7 ; dqs1_t and dqs1_c to the data on dq8 - 15 . for x32 dqs0_t and dqs0_c correspond to the data on dq0 - 7 ; dqs1_t and dqs1_c to the data on dq8 - 15 ; dqs2_t and dqs2_c to the data on dq16 - 23 ; dqs3_t and dqs3_c to the data on dq24 - 31 . dm n i n pu t input data mask: dm is the input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs_t. although dm is for input only, the dm loading shall match the dq and dqs (or dqs_c). dm0 is the input data mask signal for the data on dq0 - 7. for x16 and x32 devices, dm1 is the input data mask signal for the data on dq8 - 15. for x32 devices, dm2 is the input data mask signal for the data on d q16 - 23 and dm3 is the input data mask signal for the data on dq24 - 31. v dd1 s u pp ly core power supply 1: power supply for core . v dd 2 s u pp ly core power supply 2: power supply for core. v dd ca s u pp ly input receiver power supply: power supply for ca [n:0] , cke, cs_n, ck_t, and ck_c input buffers. v ddq s u pp ly i/o power supply: power supply for data input/output buffers. v ref(ca) s u pp ly reference voltage for ca command and control input receiver: reference voltage for all ca [n:0] , cke, cs_n, ck_t, and ck_c input buffers. v ref(dq) s u pp ly reference voltage for dq input receiver: reference voltage for all data input buffers. v ss s u pp ly ground v ssca s u pp ly ground for ca input receivers v ssq s u pp ly i/o ground zq i /o reference p in for output drive strength calibration note: data includes dq and dm.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 11 - 5.2 addressing table density 1 gb number of banks 8 bank addresses ba0 - ba 2 t refi ( s ) *2 7 . 8 x16 row addresses r0 - r1 2 column addresses *1 c0 - c 9 x 32 row addresses r0 - r1 2 column addresses *1 c0 - c 8 note s : 1. the least - significant column address c0 is not transmitted on the ca bus, and is implied to be zero . 2. t refi values for all bank refresh is - 40 c t case 8 5c . 3. row and column address values on the ca bus that are not used are dont care .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 12 - 6. block diagram d m c k _ c c k e c a 0 c l o c k b u f f e r c o m m a n d d e c o d e r a d d r e s s b u f f e r r e f r e s h c o u n t e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r m o d e r e g i s t e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 0 d a t a c o n t r o l c i r c u i t d q b u f f e r r o w d e c o r d e r d q , d q s _ t , d q s _ c c k _ t c a 9 b a n k # 7 p o w e r g n d z q
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 13 - 7. functional descripti on lpddr2 - s4 devices use a double data rate architecture on the dq pin s to achieve high speed operation. the double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per dq every clock cycle at the i/o pin s. a single read or write access for the lpddr2 - s4 effectively consists of a single 4n - bit - wide, one - clock - cycle data transfer at the internal sdram co re and four corresponding n - bit - wide, one - half - clock - cycle data transfers at the i/o pin s. read and write accesses are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. prior to normal operation, the lpddr2 device must be initialized. the following section provides detailed information covering device initialization, register definition, command description and device operation. 7.1 simplified lpddr2 state diagram lpddr2 - sdram st ate diagram provides a simplified illustration of allowed state transitions and the related commands to control them. for a complete definition of the device behavior, the information provided by the state diagram should be integrated with the truth t ables and timing specification. the truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the banks .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 14 - 7.1.1 simplified lpddr2 bus interface state diagram note: for lpddr2 - sdram in the idle state, all banks are precharged . p r e c h a r g i n g w r i t i n g w i t h a u t o p r e c h a r g e r e a d i n g w i t h a u t o p r e c h a r g e r e a d i n g w r i t i n g a c t i v e * 1 a c t i v e p o w e r d o w n a c t i v e m r r e a d i n g m r w r i t i n g i d l e p o w e r d o w n i d l e i d l e m r r e a d i n g r e s e t t i n g r e f r e s h i n g s e l f r e f r e s h i n g d e e p p o w e r d o w n p o w e r o n r e s e t t i n g m r r e a d i n g r e s e t t i n g p o w e r d o w n a u t o m a t i c s e q u e n c e c o m m a n d s e q u e n c e p o w e r a p p l i e d r e s e t m r r p d p d x b s t w r w r a w r a w r p d p d x r e s e t d p d x m r r m r w m r r p d p d x r d r d b s t d p d s r e f s r e f x r e f a c t r d a r d a p r , p r a p r ( a ) = p r e c h a r g e ( a l l ) a c t = a c t i v a t e w r ( a ) = w r i t e ( w i t h a u t o p r e c h a r g e ) r d ( a ) = r e a d ( w i t h a u t o p r e c h a r g e ) b s t = b u r s t t e r m i n a t e r e s e t = r e s e t i s a c h i e v e d t h r o u g h m r w c o m m a n d m r w = m o d e r e g i s t e r w r i t e m r r = m o d e r e g i s t e r r e a d p d = e n t e r p o w e r d o w n p d x = e x i t p o w e r d o w n s r e f = e n t e r s e l f r e f r e s h s r e f x = e x i t s e l f r e f r e s h d p d = e n t e r d e e p p o w e r d o w n d p d x = e x i t d e e p p o w e r d o w n r e f = r e f r e s h p r , p r a
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 15 - 7.2 power - up, initialization, and power - off the lpddr2 devices must be powered up and initialized in a predefined man ner. operational procedures other than those specified may result in undefined operation . 7.2.1 power ramp and device initialization the following sequence shall be used to power up an lpddr2 device. unless specified otherwise, these steps are mandatory . 1. power ramp while applying power (after ta), cke shall be held at a logic low level ( 0. 2 x v ddca ), all other inputs shall be between v il min and v ih max. the lpddr2 device will only guarantee that outputs are in a high impedance state while cke is held low. on or before the completion of the power ramp (tb) cke must be held low. dq, dm, dqs _ t and dqs_c voltage levels must be between v ssq and v ddq during voltage ramp to avoid latchup. ck_t, ck_c, cs_n, and ca input levels must be between v ssca and v ddca duri ng voltage ramp to avoid latch - up. the following conditions apply: ta is the point where any po wer supply first reaches 300mv. after ta is reached, v dd1 must be greater than v dd2 - 200mv. after ta is reached, v dd1 and v dd2 must be greater than v ddca - 200 mv. after ta is reached, v dd1 and v dd2 mus t be greater than v ddq - 200mv. after ta is reached, v ref must always be less than all other supply voltages. the voltage difference between any of v ss , v ssq , and v ssca pin s may not exceed 100mv. the above conditio ns apply between ta and power - off (controlled or uncontrolled). tb is the point when all supply voltages are within their respective min/max operating conditions. reference voltages shall be within their respective min/max operating conditions a minimum o f 5 clocks before cke goes high. for supply and reference voltage operating conditions, see 8 .2.1.1 recommended dc operating conditions table. power ramp duration t init0 (tb - ta) must be no greater than 20 ms . 2. cke and clock beginning at tb, cke must remain low for at least t init1 = 100 ns , after which it may be asserte d high. clock must be stable at least t init2 = 5 x t ck prior to the first low to high transition of cke (tc). cke, cs_n and ca inputs must observe setup and hold time (t is , t ih ) requirements with respect to the first rising clock edge (as well as to the su bsequent falling and rising edges). the clock period shall be within the range defined for t ckb (18 ns to 100 ns ), if any mode register reads are performed. mode register writes can be sent at normal clock operating frequencies so long as all ac timings are met. furthermore, some ac parameters (e.g. t d q sck ) may have relaxed timings (e.g. t dqsckb ) before the system is appropriately configured. while keeping cke high, issue nop commands for at least t init3 = 200 s . (td).
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 16 - 3. reset command after t init3 is satisfied, a mrw(reset) command shall be issued (td). the memory controller may optionally issue a precharge - all command prior to the mrw reset command. wait for at least t init4 = 1 s while keeping cke asserted and issuing nop commands. 4 . mode regis ters reads and device auto - initialization (dai) polling: after t init4 is satisfied (te) only mrr commands and power - down entry/exit commands are allowed. therefore, after te, cke may go low in accordance to power - down entry and exit specificatio n (see section 7.4.25 power - d own ) . the mrr command may be used to poll the dai - bit to acknowledge when device auto - initialization is complete or the m emory controller shall wait a minimum of t init5 before proceeding. as the memory output buffers are not properly configured yet, some ac parameters may have relaxed timings before the system is appropriately configured. after the dai - bit (mr#0, dai) is set to zero dai complete by the memory device, the device is in idle state (tf). the state of the dai status bit can be determined by an mrr command to mr#0. the lpddr2 sdram device will set the dai - bit no later than t init5 (10 s ) after the reset comm and. the memory controller shall wait a minimum of t init5 or until the dai - bit is set before proceeding. after the dai - bit is set, it is recommended to determine the device type and other device characteristics by issuing mrr commands (mr0 device informa tion etc.). 5 . zq calibration: after t init5 (tf), an mrw zq initialization calibration command may be issued to the memor y (mr10) . this command is used to calibrate the lpddr2 output drivers (ron) over process, voltage, and temperature. optionally, the mrw zq initialization calibration command will update mr0 to indicate rzq pin connection. in systems in which more than one lpddr2 device exists on the same bus, the controller must not overlap zq calibration commands. the device is ready f or normal oper a tion after t zqinit . 6 . normal operation: after t zqinit (tg ), mrw co mmands may be used to properly configure the memory, for example the output buffer driver strength, latencies etc. specifically, mr1, mr2, and mr3 shall be set to configure the memory for the target frequency and memory configuration. the lpddr2 device will now be in idle state and ready for any valid command. after tg, the clock frequency may be changed according to the clock frequency change procedure described in section 7.4.27 input c lock s top and f requency c hange .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 17 - 7.2.2 timing parameters for i nitialization symbol value unit comment min max t init0 20 ms maximum power ramp time t init1 100 ns minimum cke low time after completion of power ramp t init2 5 t ck minimum stable clock before first cke high t init3 200 s minimum idle time after first cke assertion t init4 1 s minimum idle time after reset command t init5 10 s maximum duration of device auto - initialization t zqinit 1 s zq initial calibration for lpddr2 - s4 t ckb 18 100 ns clock cycle time during boot 7.2.3 power ramp and initialization sequence * m i d l e v e l o n c a b u s m e a n s : v a l i d n o p t i n i t 2 = 5 t c k ( m i n ) t i n i t 3 = 2 0 0 s ( m i n ) t i n i t 1 = 1 0 0 n s ( m i n ) t i n i t 0 = 2 0 m s ( m a x ) t i n i t 4 = 1 s ( m i n ) t i s c k e t i n i t 5 t a t b t c t g t e t d r e s e t z q c v a l i d c k _ t / c k _ c s u p p l i e s c k e c a * d q p d t f m r r t z q i n i t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 18 - 7.2.4 initialization after reset (without power ramp) if the reset command is issued outside the power up initialization sequence, the reinitialization procedure shall begin with step 3 (td) . 7.2.5 power - off sequence the following sequence shall be used to power off the lpddr2 device. while removing power, cke shall be held at a logic low level ( 0.2 x v ddca ), all other inputs shall be between v il min and v ih max. the lpddr2 device will only guarantee that outputs are in a high impedance state while cke is held low. dq, dm, dqs_t and dqs _c vo ltage levels must be between v ssq and v ddq during power off sequence to avoid latch - up. ck_t, ck_c, cs_n and ca input levels must be between v ssca and v ddca during power off sequence to avoid latch - up. tx is the point where any power supply decreases under its minimum value specified in 8 .2.1.1 recommended dc operating conditions table . tz is the point where all power supplies are below 300 mv. afte r tz, the device is powered off . the time between tx and tz (t poff ) shall be less than 2 s . the following conditions apply: between tx and tz, v dd1 must be greater than v dd2 - 200 mv. between tx and tz, v dd1 and v dd2 must be greater than v ddca - 200 mv. between tx and tz, v dd1 and v dd2 must be greater than v ddq - 200 mv. between tx and tz, v ref must always be less than all other supply voltages. the voltage difference between any of v ss , v ssq , and v ssca pin s may not exceed 100 mv. for supply and reference voltage operating conditions, see 8 .2.1.1 recommended dc operating conditions table . 7.2.6 timing parameters power - off symbol value unit comment min max t poff - 2 s maximum power - off ramp time 7.2.7 uncontrolled power - off sequence the following sequence shall be used to power off the lpddr2 devic e under uncontrolled condition. tx is the point where any power supply decreases under its minimum value specified in the dc operating condition table. after turning off all power supplies, any power supply current capacity must be zero, except for any static charge remaining in the system. tz is the point where all power supply first reaches 300 mv. after tz, the device is powered off. the time between tx and tz ( t poff ) shall be less than 2 s . the relative levels between supply voltages are uncontrolled during this period. v dd1 and v dd2 shall decrease with a slope lower than 0.5 v/ s between tx and tz. uncontrolled power off sequence can be applied only up to 400 times in the life of the device.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 19 - 7.3 mode register definition 7.3.1 mode register assignment and definition each register is denoted as r if it can be read but not written, w if it can be written but not read, and r/w if it can be read and written. mode register read command shall be used to read a register. mode registe r write command shall be used to write a register . 7.3.1.1 mode register assignment mr# ma [ 7 : 0 ] f u nct ion a cce ss op7 op6 op5 op4 op3 op2 op1 op0 0 0 0 h device info . r (rfu ) rzqi dnvi d i da i 1 0 1 h device f eature 1 w n wr (for ap ) wc b t b l 2 0 2 h device f eature 2 w (rfu ) rl & w l 3 0 3 h i/o config - 1 w (rfu ) d s 4 0 4 h refresh rate r tu f (rfu ) refresh rate 5 0 5 h basic confi g - 1 r l pddr2 man u f a ctur e r i d 6 0 6 h basic config - 2 r r e v i sion id 1 7 0 7 h basic config - 3 r r e v i sion id 2 8 0 8 h basic confi g - 4 r i /o wi d t h de ns it y t y pe 9 0 9 h t e st m o d e w v e n dor - s pecific t es t mo de 1 0 0a h i / o ca l ibratio n w ca l ibratio n c od e 11 - 1 5 0 b h ~ 0f h (r es erved ) - (rfu ) 1 6 1 0 h p as r _bank w bank mask 1 7 1 1 h p asr _ se g w se g m e n t mask 18 - 19 12 h ~ 13 h (reserved) - (rfu) 20 - 31 14h C 1fh reserved for nvm 32 20h dq calibration pattern a r see 7.4.21.2 dq calibration 33 - 39 21 h ~ 27 h (do not use) - 40 28h dq calibration pattern b r see 7.4.21.2 dq calibration 41 - 47 29 h ~ 2f h (do not use) - 48 - 62 30 h ~ 3e h (reserved) - (rfu) 63 3fh reset w x 64 - 126 40 h ~ 7e h (reserved) - (rfu) 127 7fh (do not use) - 128 - 190 80 h ~ be h (reserved for vendor use) - (rfu) 191 bfh (do not use) - 192 - 254 c0 h ~ fe h (reserved for vendor use) - (rfu) 255 ffh (do not use) - note s : 1. rfu bits shall be set to 0 during mode register writes . 2. rfu bits shall be read as 0 during mode register reads . 3. all mode registers that are specified as rfu or write - only shall return undefined data when read and dqs shall be toggled . 4. all mode registers that are specified as rfu shall not be written . 5. writes to read - only registers shall have no impact on the functionality of the device.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 20 - 7.3.2 m r0_device information (ma[7:0] = 00h) op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 (rfu ) rzqi dnvi d i d a i dai ( d evice auto - initia l ization s t a t u s ) r ead - o nl y op0 0 b : dai co m plete 1 b : dai sti l l in progr e s s di (device inform a t i on ) r ead - o nl y op1 0 b : s4 sdram dnvi (data not valid information) r ead - o nl y op 2 0 b : lpddr2 sdram will not implement dnv functionalit rzqi (built in self test for rzq information) r ead - o nl y op [ 4:3] 00 b : rzq self test not executed. 01 b : zq - pin may connect to v ddca or float 10 b : zq - pin may short to gnd 11 b : zq - pin self test completed, no error condition detected (zq - pin may not connect to v ddca or float nor short to gnd) note s : 1. rzqi will be set upon completion of the mrw zq initialization calibration command . 2. if zq is connected to v ddca to set default calibration by user, op[4:3] shall be read as 01. if user does not want to connect zq pin to v ddca , but op[4:3] is read as 01 or 10, it might indicate a zq - pin assembly error. it is recommended that the assembly error being corrected fi rst . 3. in the case of possible assembly error (either op[4:3]=01 or op[4:3]=10 as defined above), the lpddr2 device will default to f ac tory trim settings for ron, and will ignore zq calibration commands. in either case, the system may not function as intende d . 4. in the case of the zq self - test returning a value of 11b, this result indicates that the device has detected a resistor connection to the zq pin . however, this result cannot be used to validate the zq resistor value or that the zq resistor tolerance mee ts the specified limits (i.e. , 240 o hm 1%) . 5. if the zq resistor is absent from the system, zq shall be connected to v ddca . in this case, the lpddr2 device shall ignore zq calibration commands and the device will use the default calibration settings. 7.3.3 mr1_d evice feature 1 (ma[7:0] = 01h) op 7 op6 op5 op 4 op 3 op 2 op1 op0 nwr (for ap) w c b t bl b l write - only op [ 2 : 0 ] 0 10 b : b l 4 ( d efault) 0 1 1 b : bl8 1 00 b : bl16 a l l oth e rs : reserved b t write - only op3 0 b : seq u entia l (d e f a ult) 1 b : i n t e r l eave d wc write - only op4 0 b : w ra p ( d efault) 1 b : no wrap (allowed for sdram bl4 only) nwr write - only op [ 7:5 ] 0 01 b : nwr=3 (default) 0 1 0 b : nwr=4 0 11b : nwr=5 1 0 0 b : nwr=6 101 b : nwr=7 11 0 b : nwr=8 all others: reserved 1 note: 1. programmed value in nwr register is the number of clock cycles which determines when to start internal precharge operation for a write burst with ap enabled. it is determined by ru(t wr /t ck ) .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 21 - 7.3.3.1 burst sequence by burst length (bl), burst type (bt), and warp control (wc) c 3 c2 c1 c0 wc bt bl bur s t c y cl e num b e r a nd b u rs t a d dr e s s se q ue n ce 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 0 b 0 b wra p a ny 4 0 1 2 3 x x 1 b 0 b 2 3 0 1 x x x 0 b n w a ny y y+ 1 y+ 2 y+ 3 x 0 b 0 b 0 b wra p seq 8 0 1 2 3 4 5 6 7 x 0 b 1 b 0 b 2 3 4 5 6 7 0 1 x 1 b 0 b 0 b 4 5 6 7 0 1 2 3 x 1 b 1 b 0 b 6 7 0 1 2 3 4 5 x 0 b 0 b 0 b i nt 0 1 2 3 4 5 6 7 x 0 b 1 b 0 b 2 3 0 1 6 7 4 5 x 1 b 0 b 0 b 4 5 6 7 0 1 2 3 x 1 b 1 b 0 b 6 7 4 5 2 3 0 1 x x x 0 b n w a ny i l legal (n o t al l o w e d ) 0 b 0 b 0 b 0 b wra p seq 16 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 b 0 b 1 b 0 b 2 3 4 5 6 7 8 9 a b c d e f 0 1 0 b 1 b 0 b 0 b 4 5 6 7 8 9 a b c d e f 0 1 2 3 0 b 1 b 1 b 0 b 6 7 8 9 a b c d e f 0 1 2 3 4 5 1 b 0 b 0 b 0 b 8 9 a b c d e f 0 1 2 3 4 5 6 7 1 b 0 b 1 b 0 b a b c d e f 0 1 2 3 4 5 6 7 8 9 1 b 1 b 0 b 0 b c d e f 0 1 2 3 4 5 6 7 8 9 a b 1 b 1 b 1 b 0 b e f 0 1 2 3 4 5 6 7 8 9 a b c d x x x 0 b i nt i l legal (n o t al l o w e d ) x x x 0 b n w a ny i l legal (n o t al l o w e d ) note s : 1. c0 input is not present on ca bus. it is implied zero . 2. for bl=4, the burst address represents c [ 1 : 0 ] . 3. for bl=8, the burst address represents c [ 2 : 0 ] . 4. for bl=16, the burst address represents c [ 3 : 0 ] . 5. for no - wrap (nw), bl4, the burst shall not cross the page boundary and shall not cross sub - page boundary. the variable y may start at any address with c0 equal to 0 and may not start at any address shown in t able below. 7.3.3.2 non wrap restrictions bus width 1gb not across full page boundary x16 3 fe, 3 ff, 000, 001 x32 1 fe, 1 ff, 00 0 , 0 0 1 not across sub page boundary x16 1 fe, 1 ff, 2 00, 2 01 x 32 none note: non - wrap bl=4 data - orders shown above are prohibited.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 22 - 7.3.4 mr2_device feature 2 (ma[7:0] = 02h) op7 op 6 op 5 o p 4 op3 op2 op 1 op0 (rfu ) rl & wl rl & wl write - only op [ 3:0 ] 0001 b : rl = 3 / wl = 1 (default) 0010 b : rl = 4 / wl = 2 0011 b : rl = 5 / wl = 2 0100 b : rl = 6 / wl = 3 0101 b : rl = 7 / wl = 4 0110 b : rl = 8 / wl = 4 all others: reserved 7.3.5 mr3_i/o configuration 1 (ma[7:0] = 03h) op7 op 6 op 5 o p 4 op3 op2 op 1 op0 (rfu) ds ds write - only op [ 3:0 ] 0 00 0 b : reserved 0 00 1 b : 3 4.3 - oh m typical 0 01 0 b : 40 - o h m typica l (d e f a ult) 0 0 1 1 b : 4 8 - ohm ty p ical 0 10 0 b : 60 - oh m typical 0 10 1 b : r e served 0 1 10 b : 8 0 - ohm ty p ical 0 1 1 1 b : 120 - ohm ty p ical a l l oth e rs : reserved 7.3.6 mr4_de vice temperature (ma[7:0] = 04h ) o p 7 o p 6 o p 5 o p 4 o p 3 o p 2 o p 1 o p 0 tuf (rfu ) sdra m r e fres h r a te sdram refresh rate read - only op [ 2:0 ] 0 00 b : sdra m l ow t e m p erature op e rating l i m i t excee d ed 0 01 b : 4x t refi , 4x t refi pb , 4x t refw 0 10 b : 2x t refi , 2 x t refi pb , 2x t refw 0 1 1 b : 1x t refi , 1 x t refi pb , 1x t refw ( 85 c ) 100 b : reserved 1 01 b : 0.25x t refi , 0.25x t refi pb , 0.25x t refw , do not de - rate sdram ac timing 1 1 0 b : 0.25x t refi , 0.25x t refi pb , 0.25x t refw , de - rate sdram ac timing 11 1 b : sdram hi g h t e m p erature op e rating l i m i t excee d ed temperature update flag (tuf) read - only op7 0 b : op [ 2 : 0 ] val ue h as no t c h ang e d since l a st read of m r 4 . 1 b : op [ 2 : 0 ] val ue h as c h an g ed since l a st rea d o f mr4 . note s : 1. a mode register read from mr4 will reset op7 to 0 . 2. op7 is reset to 0 at power - up . 3. if op2 equals 1 , the device temperature is greater than 85 c . 4. op7 is set to 1 if op2:op0 has changed at any time since the last read of mr4 . 5. lpddr2 might not operate properly when op[2:0] = 000 b or 111 b . 6. for specified operating temperature range and maximum operating temperature, refer to operating temperature conditions table. 7. lpddr2 devices must be derated by adding 1.875 ns to the following core timing parameters: t rcd , t rc , t ras , t rp , and t rrd . t dqsck shall be de - rated according to the t dqsck de - rating value in lpddr2 ac timing table. prevailing clock frequency spec and related setup and hold timi ngs shall remain unchanged . 8. the recommended frequency for reading mr4 is provided in temperature sensor section.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 23 - 7.3.7 mr5_basic configuration 1 (ma [ 7:0 ] = 05h) op7 op6 op5 op4 op3 op2 op1 op0 lpddr2 manufacturer id lp d dr2 manufacturer i d read - only op [ 7 : 0 ] 0000 1000 b : winbond 7.3.8 mr6_basic configuration 2 (ma[7:0] = 06h) op7 op6 op5 op4 op3 op2 op1 op0 rev i s i on id1 revision id 1 read - only op [ 7 : 0 ] 0 00 0 000 0 b : a - v e rsion note: mr 6 is v endor s pecific. 7.3.9 mr7_basic configuration 3 (ma[7:0] = 07h) op7 op6 op5 op4 op3 op2 op1 op0 rev i s i on id 2 revision id 2 read - only op [ 7 : 0 ] 0 00 0 000 0 b : a - v e rsion note: mr7 is v endor s pecific . 7.3.10 mr8_basic configuration 4 (ma[7:0] = 08h) op7 op6 op5 op4 op3 op2 op1 op0 i/o wi d t h density t ype t y pe read - only op [ 1 : 0 ] 0 0 b : s 4 sdra m d e nsit y read - only op [ 5 : 2 ] 0 10 0 b : 1g b i / o wi d th read - only op [ 7 : 6 ] 0 0 b : x32 0 1 b : x16 7.3.11 mr9_test mode (ma[7:0] = 09h) op7 op6 op5 op4 op3 op2 op1 op0 v en d or - specific t es t mo de
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 24 - 7.3.12 mr10_calibration (ma[7:0] = 0ah) op7 op6 op5 op4 op3 op2 op1 op0 calibration code calibration code write - only op [ 7 : 0 ] 0xff: calibration command after initialization 0xab: long calibration 0x56: short calibration 0xc3: zq reset others: reserved note s : 1. host processor shall not write mr10 with reserved values . 2. lpddr2 devices shall ignore calibration command when a reserved value is written into mr10 . 3. see ac timing table for the calibration latency . 4. if zq is connected to v ssca through rzq, either the zq calibration function (see section 7.4.24 mode register write zq calibration command ) or default calibration (through the zqreset command) is supported. if zq is connecte d to v ddca , the device operates with default calibration, and zq calibration commands are ignored. in both cases, the zq connection shall not change after power is applied to the device . 5. optionally, the mrw zq initialization calibration command will update mr0 to indicate rzq pin connec tion. 7.3.13 mr16_pasr_bank mask (ma[7:0] = 10h) op7 op6 op5 op4 op3 op2 op1 op0 s 4 sdra m bank mask ( 8 - bank ) bank [ 7 :0 ] mask write - only op [ 7 : 0 ] 0 b : refresh enable to the bank (=unmasked, default) 1 b : refresh blocked (=masked) op bank mask 8 - bank s4 sdram 0 xxxxxxx1 bank 0 1 xxxxxx1x bank 1 2 xxxxx1xx bank 2 3 xxxx1xxx bank 3 4 xxx 1 xxx x bank 4 5 xx 1 xxx x x bank 5 6 x 1 xxx x xx bank 6 7 1 xxx x xxx bank 7
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 25 - 7.3.14 mr17_pasr_segment mask (ma[7:0] = 11h) op7 op6 op5 op4 op3 op2 op1 op0 segment mask segment [7:0] mask write - only op [ 7 : 0 ] 0 b : refresh enable to the segment (=unmasked, default) 1 b : refresh blocked (=masked) segment op segment mask r[12:10] 0 0 xxxxxxx1 000 b 1 1 xxxxxx1x 001 b 2 2 xxxxx1xx 010 b 3 3 xxxx1xxx 011 b 4 4 xxx 1 xxx x 100 b 5 5 xx 1 xxx x x 101 b 6 6 x 1 xxx x xx 110 b 7 7 1 xxx x xxx 111 b 7.3.15 mr32_dq calibration pattern a (ma[7:0] = 20h) reads to mr32 return dq calibration pattern a. see section 7.4.21.2 dq calibration . 7.3.16 mr40_dq calibration pattern b (ma[7:0] = 28h) reads to mr40 return dq calibration pattern b. see section 7.4.21.2 dq calibration . 7.3.17 mr63_reset (ma[7:0] = 3fh): mrw only op7 op6 op5 op4 op3 op2 op1 op0 x for additonal information on mrw reset see section 7.4.22 mode register write command .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 26 - 7.4 command definitions and timing diagrams 7.4.1 activate command the sdram activate command is issued by holding cs_n low, ca0 low, and ca1 high at the rising edge of the clock. the bank addresses are used to select the desired bank. the row address es are used to determine which row to activate in the selected bank. the activate command must be applied before any read or write operation can be executed. the lpddr2 sdram can accept a read or write command at time t rcd after the activate command is sent. once a bank has been activated it must be precharged before another activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , re spectively. the minimum time interval between successive activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between activate commands to different banks is t rrd . certain restrictions on op eration of the 8 - bank devices must be observed. there are two rules. one for restricting the number of sequential activate commands that can be issued and another for allowing more time for ras precharge for a precharge all command. the rules are as follow s: 8 - bank device sequential bank activation restriction: no more than 4 banks may be activated (or refreshed, in the case of refpb) in a rolling tfaw window. converting to clocks is done by dividing t faw [n s ] by t ck [n s ], and rounding up to next integer val ue . as an example of the rolling window, if ru{ (t faw / t ck ) } is 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued at or between clock n+1 and n+9. refpb also counts as bank - activation for the purposes of t faw . 8 - bank device precharge all allowance: t rp for a precharge all command for an 8 - bank device shall equal t rpab , which is greater than t rppb . 7.4.1.1 activate c ommand c ycle: t rcd = 3, t rp = 3, t rrd = 2 note: a precharge - all command uses t rpab timing, while a single bank precharge command uses t rppb timing. in this figure, t rp is used to denote either an all - bank precharge or a single bank precharge t 0 t 1 t 2 t 3 t n t n + 3 t n + 2 t n + 1 c k _ t / c k _ c c a 0 - 9 [ c m d ] a c t i v a t e n o p a c t i v a t e r e a d r a s - c a s d e l a y = t r c d r a s - r a s d e l a y t i m e = t r r d b a n k p r e c h a r g e t i m e = t r p b a n k a c t i v e = t r a s r o w c y c l e t i m e = t r c r e a d b e g i n s p r e c h a r g e n o p n o p a c t i v a t e b a n k a r o w a d d r r o w a d d r b a n k b r o w a d d r r o w a d d r b a n k a c o l a d d r c o l a d d r b a n k a b a n k a r o w a d d r r o w a d d r
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 27 - 7.4.1.2 t faw t iming note : t faw is f or 8 - bank devices only . 7.4.1.3 command input setup and hold timing note : setup and hold conditions also apply to the cke pin . see section related to power down for timing diagrams related to the cke pin . c a 0 - 9 [ c m d ] c k _ t / c k _ c t z + 2 t z + 1 t z t r r d t f a w t r r d t y + 2 t y + 1 t y t x t x + t m + t m t n + t n b a n k e b a n k e t r r d b a n k a b a n k a b a n k b b a n k b b a n k c b a n k c b a n k d b a n k d a c t n o p n o p n o p n o p a c t a c t a c t a c t t 0 n o p c k _ t / c k _ c c a 0 - 9 [ c m d ] t 1 t 2 t 3 c s _ n c o m m a n d n o p c o m m a n d t i s t i h t i s t i h t i h t i h t i s t i s c a r i s e c a r i s e c a r i s e c a r i s e c a f a l l c a f a l l c a f a l l c a f a l l v i l ( a c ) v i l ( d c ) v i h ( a c ) v i h ( d c ) h i g h o r l o w ( b u t a d e f i n e d l o g i c l e v e l )
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 28 - 7.4.1.4 cke input setup and hold timing note s : 1. after cke is registered low, cke signal level shall be maintained below v ilcke for t cke specification (low pulse width) . 2. after cke is registered high, cke signal level shall be maintained above v ihcke for t cke specification (high pulse width) . 7.4.2 read and write a ccess m odes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting cs_n low, ca0 high, and ca1 low at the rising edge of the clock. ca2 must also be define d at this time to determine whether the access cycle is a read operation (ca2 high) or a write operation (ca2 low). the lpddr2 sdram provides a fast column access operation. a single read or write command will initiate a burst read or write operation on s uccessive clock cycles. a new burst access must not interrupt the previous 4 - bit burst operation in case of bl = 4 setting. in case of bl = 8 and bl = 16 settings, reads may be interrupted by reads and writes may be interrupted by writes provided that this occurs on even clock cycles after the read or write command and t ccd i s met. 7.4.3 burst read c ommand the burst read command is initiated by having cs_n low, ca0 high, ca1 low and ca2 high at the rising edge of the clock. the command address bus inputs, ca 5r - ca6r and ca1f - ca9f, determine the starting column address for the burst. the read latency (rl) is defined from the rising edge of the clock on which the read command is issued to the rising edge of the clock from which the t dqsck delay is measured. the first valid datum is available rl * t ck + t dqsck + t dqsq after the rising edge of the clock where the read command is issued. the data strobe output is driven low t rpre before the first rising valid strobe edge. the first bit of the burst is synchronized w ith the first rising edge of the data strobe. each subsequent data - out appears on each dq pin edge aligned with the data strobe. the rl is programmed in the mode registers. timings for the data strobe are measured relative to the crosspoint of dqs _t and its complement, dqs _c . h i g h o r l o w ( b u t a d e f i n e d l o g i c l e v e l ) t 0 t 1 t x t x + 1 c k _ t / c k _ c c k e t i s c k e t i s c k e t i h c k e t i h c k e v i h c k e v i l c k e v i h c k e v i l c k e
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 29 - 7.4.3.1 data o utput ( r ead) t iming (t dqsckmax ) note s : 1. t dqsck may span multiple clock period s. 2. an effective burst length of 4 is shown . d q d q s _ c c k _ t c k _ c r l - 1 r l d q s _ t d q s _ c r l + b l / 2 q q q q t q h t h z ( d q ) t d q s q m a x t d q s q m a x t d q s c k m a x t l z ( d q ) t l z ( d q s ) t r p r e t h z ( d q s ) t r p s t t q h t c h t c l d q s _ t t q s h t q s l
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 30 - 7.4.3.2 data o utput ( r ead) t iming (t dqsckmin ) note: an effective burst length of 4 is shown . 7.4.3.3 burst r ead: rl = 5 , bl = 4 , t dqsck > t ck q q q q t d q s q m a x t d q s c k m i n r l + b l / 2 t h z ( d q s ) t r p s t t q h t h z ( d q ) t q h t l z ( d q ) t d q s q m a x t r p r e d q t l z ( d q s ) c k _ t c k _ c r l - 1 r l t c h t c l d q s _ t d q s _ c d q s _ c d q s _ t t q s l t q s h c k _ t / c k _ c c a 0 - 9 [ c m d ] n o p n o p n o p n o p n o p n o p n o p n o p r e a d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 d q s _ c d q s t d q s c k r l = 5 b a n k a c o l a d d r c o l a d d r d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 31 - 7.4.3.4 burst r ead: rl = 3, bl = 8, t dqsck < t ck 7.4.3.5 lpddr2: t dqsckdl t iming note: t dqsckdlmax is defined as the maximum of abs(t dqsckn - t dqsckm ) for any {t dqsckn ,t dqsckm } pair within any 32 ms rolling window. c k _ t / c k _ c c a 0 - 9 [ c m d ] n o p n o p n o p n o p n o p n o p n o p n o p r e a d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 d q s _ c d q s t d q s c k r l = 3 b a n k a c o l a d d r c o l a d d r d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 d q s _ t c a 0 - 9 [ c m d ] d q s t m + 8 3 2 m s m a x i m u m r l = 5 c k _ t / c k _ c d q s _ c d q s _ t d o u t a 3 t m + 7 t m + 6 t m + 5 t m + 4 t m + 3 t m + 2 t m + 1 t m t d q s c k m d o u t a 2 d o u t a 1 d o u t a 0 t n + 8 r l = 5 d o u t a 3 t n + 7 t n + 6 t n + 5 t n + 4 t n + 3 t n + 2 t n + 1 t d q s c k n d o u t a 2 d o u t a 1 d o u t a 0 t n t d q s c k d l = l t d q s c k n C t d q s c k m l c o l a d d r r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p r e a d c o l a d d r c o l a d d r c o l a d d r n o p
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 32 - 7.4.3.6 lpddr2: t dqsckdm t iming note: t dqsckdmmax is defined as the maximum of abs(t dqsckn - t dqsckm ) for any {t dqsckn ,t dqsckm } pair within any 1.6 s rolling window. 7.4.3.7 lpddr2: t dqsckds t iming note: t dqsckdsmax is defined as the maximum of abs(t dqsckn - t dqsckm ) for any {t dqsckn ,t dqsckm } pair for reads within a consecutive burst within any 160 ns rolling window c a 0 - 9 [ c m d ] d q s t m + 8 1 . 6 s m a x i m u m r l = 5 c k _ t / c k _ c d q s _ c d q s _ t t m + 7 t m + 6 t m + 5 t m + 4 t m + 3 t m + 2 t m + 1 t m t d q s c k m t n + 8 r l = 5 t n + 7 t n + 6 t n + 5 t n + 4 t n + 3 t n + 2 t n + 1 t d q s c k n d o u t a 0 t n t d q s c k d m = l t d q s c k n C t d q s c k m l n o p c o l a d d r r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p r e a d c o l a d d r c o l a d d r c o l a d d r n o p d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 c a 0 - 9 [ c m d ] d q s t m + 8 1 6 0 n s m a x i m u m r l = 5 c k _ t / c k _ c d q s _ c d q s _ t t m + 7 t m + 6 t m + 5 t m + 4 t m + 3 t m + 2 t m + 1 t m t d q s c k m t n + 8 r l = 5 t n + 7 t n + 6 t n + 5 t n + 4 t n + 3 t n + 2 t n + 1 t d q s c k n d o u t a 0 t n t d q s c k d s = l t d q s c k n C t d q s c k m l n o p c o l a d d r r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p r e a d c o l a d d r c o l a d d r c o l a d d r n o p d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 n o p
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 33 - 7.4.3.8 burst r ead f ollowed by b urst w rite: rl = 3, wl = 1, bl = 4 the minimum time from the burst read command to the burst write command is defined by the read latency (rl) and the burst length (bl). minimum read to write latency is rl + ru(t dqsckmax /t ck ) + bl/2 + 1 - wl clock cycles. note that if a read burst is truncated with a burst terminate (bst) command, the effective burst length of the truncated read burst should be used as bl to calculate the minimum read to write delay . 7.4.3.9 seamless b urst r ead: rl = 3, bl= 4, t ccd = 2 the seamless burst read operation is supported by enabling a read command at every other clock for bl = 4 operation, every 4 clocks for bl = 8 opera tion, and every 8 clocks for bl=16 operation. for lpddr2 - sdram, this operation is allowed regardless of whether the accesses read the same or different banks as long as the banks are activated. c k _ t / c k _ c c a 0 - 9 [ c m d ] n o p n o p n o p n o p n o p w r i t e n o p n o p r e a d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 d q s _ c d q s t d q s c k r l = 3 b a n k a c o l a d d r c o l a d d r d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d i n a 0 d i n a 1 d i n a 2 w l = 1 t d q s s m i n b l / 2 b a n k a c o l a d d r c o l a d d r d q s _ t c k _ t / c k _ c c a 0 - 9 [ c m d ] n o p r e a d n o p n o p n o p n o p n o p n o p r e a d d q s _ c d q s r l = 3 b a n k n c o l a d d r a c o l a d d r a d o u t a 0 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t c c d = 2 b a n k n c o l a d d r b c o l a d d r b d q s _ t d o u t a 1 d o u t a 2 d o u t a 3 d o u t b 0 d o u t b 1 d o u t b 2 d o u t b 3
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 34 - 7.4.4 reads i nterrupted by a r ead for lpddr2 - s4 device, burst read can be interrupted by another read on even clock cycles after the read command, provided that t ccd is met . 7.4.4.1 read b urst i nterrupt e xample: rl = 3, bl= 8, t ccd = 2 note s : 1. for lpddr2 - s4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16 . 2. for lpddr2 - s4 devices, read burst interrupt may occur on any clock cycle after the intial read command, provided that t ccd is met . 3. reads can only be interrupted by other reads or the bst command. 4. read burst inte rruption is allowed to any bank inside dram. 5. read burst with auto - precharge is not allowed to be interrupted. 6. the effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read. 7.4.5 burst write o peration the burst write command is initiated by having cs_n low, ca0 high, ca1 low and ca2 low at the rising edge of the clock. the command address bus inputs, ca5r - ca6r and ca1f - ca9f, determine the starting column address for the burst. the write latency (wl) is defined from the rising edge of the clock on which the write command is issued to the rising edge of the clock from which the t dqss delay is measured. the first valid dat a must be driven wl * t ck + t dqss from the rising edge of the clock fr om which the write command is issued. the data strobe signal (dqs) should be driven low t wpre prior to the data input. the data bits of the burst cycle must be applied to the dq pin s t ds prior to the respective edge of the dqs_t , dqs_c and held valid until t dh after that edge. the burst data are sampled on successive edges of the dqs_t , dqs_c until the burst length is completed, which is 4, 8, or 16 bit burst. for lpddr2 - sdram devices, t wr must be satisfied before a precharge command to the same bank may b e issued after a burst write operation. i nput timings are measured relative to the crosspoint of dqs_t and its complement, dqs_c. r l = 3 t c c d = 2 n o p r e a d n o p n o p n o p n o p n o p n o p c o l a d d r a d o u t a 0 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 b a n k n c o l a d d r a r e a d b a n k n c o l a d d r b c o l a d d r b c a 0 - 9 [ c m d ] d q s c k _ t / c k _ c d q s _ c d q s _ t d o u t a 1 d o u t a 2 d o u t a 3 d o u t b 0 d o u t b 1 d o u t b 2 d o u t b 3 d o u t b 4 d o u t b 5
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 35 - 7.4.5.1 data i nput ( w rite) t iming 7.4.5.2 burst w rite: wl = 1, bl= 4 d q s _ c d q s _ t d q d m d q s _ t d q s _ c d d d d d m i n d m i n d m i n d m i n t d q s h t d q s l t w p r e t w p s t t d h t d s t d s v i h ( d c ) v i l ( d c ) v i h ( d c ) v i l ( d c ) v i l ( a c ) v i h ( a c ) v i h ( a c ) v i l ( a c ) t d h c a 0 - 9 [ c m d ] d q s _ c c k _ t / c k _ c d q s d q s d q s _ c t 0 t 1 t 2 t 3 t 4 t x t x + 1 t y t y + 1 t r p t w r t d s h t d s h t d s s t d s s t w r b a n k a c o l a d d r c o l a d d r b a n k a r o w a d d r b a n k a r o w a d d r n o p n o p n o p n o p n o p n o p w r i t e p r e c h a r g e a c t i v a t e d i n a 0 d i n a 1 d i n a 2 d i n a 3 d i n a 0 d i n a 1 d i n a 2 d i n a 3 t d q s s m a x t d q s s m i n c o m p l e t i o n o f b u r s t w r i t e c a s e 1 : w i t h t d q s s ( m a x ) c a s e 2 : w i t h t d q s s ( m i n ) w l = 1 w l = 1 d q s _ t d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 36 - 7.4.5.3 burst w irte f ollowed by b urst r ead: rl = 3, wl= 1, bl= 4 note s : 1. the minimum number of clock cycles from the burst write command to the burst read command for any bank is [wl + 1 + bl/2 + ru( t wtr /t ck )] . 2. t wtr starts at the rising edge of the clock after the last valid input datum . 3. if a write burst is truncated with a burst terminate (bst) command, the effective burst length of the truncated write burst s hould be used as bl to calculate the minimum write to r ead delay. 7.4.5.4 seamless b urst w rite: wl= 1, bl = 4, t ccd = 2 note: the seamless burst write operation is supported by enabling a write command every other clock for bl = 4 operation, every fou r clocks for bl = 8 operation, or every eight clocks for bl = 16 operation. this operation is allowed regardless of same or different banks as long as the banks are activated c k _ t / c k _ c c a 0 - 9 [ c m d ] n o p r e a d n o p n o p n o p n o p n o p n o p w r i t e d q s _ c d q s t w t r b a n k m c o l a d d r a c o l a d d r a d i n a 0 d i n a 1 d i n a 2 d i n a 3 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 w l = 1 b a n k n c o l a d d r b c o l a d d r b r l = 3 d q s _ t c k _ t / c k _ c c a 0 - 9 [ c m d ] n o p w r i t e n o p n o p n o p n o p n o p n o p w r i t e d q s _ c d q s w l = 1 b a n k m c o l a d d r a c o l a d d r a d i n a 0 d i n a 1 d i n a 2 d i n a 3 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t c c d = 2 b a n k n c o l a d d r b c o l a d d r b d i n b 0 d i n b 1 d i n b 2 d i n b 3 d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 37 - 7.4.6 writes i nterrupted by a w rite for lpddr2 - s4 devices, burst writes can only be interrupted by another write on even clock cycles after the write command , provided that t ccd (min) is met . 7.4.6.1 write b urst i nterrupt t iming: wl = 1, bl = 8 , t ccd = 2 note s : 1. for lpddr2 - s4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16 . 2. for lpddr2 - s4 devices, write burst interrupt may only occur on even clock cycles after the previous write commands, provided that t ccd(min) is met . 3. writes can only be interrupted by other writes or the bst command. 4. write bur st interruption is allowed to any bank inside dram. 5. write burst with auto - precharge is not allowed to be interrupted. 6. the effective burst length of the first write equals two times the number of clock cycles between the first write and the int errupting wri te . 7.4.7 burst terminate the burst terminate (bst) command is initiated by having cs_n low, ca0 high, ca1 high, ca2 low, and ca3 low at the rising edge of clock. a burst teminate command may only be issued to terminate an active read or write burst. therefore, a burst terminate command may only be issued up to and including bl/2 - 1 clock cycles after a read or write command. the effective burst length of a read or write command truncated by a bst command is as follows: effective burst length = 2 x {number of c lock cycles from the read or write command to the bst command} note that if a read or write burst is truncated with a burst terminate (bst) command, the effective burst length of the truncated burst should be used as bl to calculate the minimum read to w rite or write to read delay. the bst command only affects the most recent read or write command. the bst command truncates an ongoing read burst rl * t ck + t dqsck + t dqsq after the rising edge of the clock where the burst terminate command is issued. the bst command truncates an on going write burst wl * t ck + t dqss after the rising edge of the clock where the burst terminate command is issued. for lpddr2 - s4 devices, the 4 - bit prefetch architecture allows the bst command to be issued on an even number of clock cycles after a write or read command. therefore, the effective burst length of a read or write command truncated by a bst command is an integer multiple of 4 . c k _ t / c k _ c c a 0 - 9 [ c m d ] n o p w r i t e n o p n o p n o p n o p n o p n o p w r i t e d q s _ c d q s w l = 1 b a n k m c o l a d d r a c o l a d d r a d i n a 0 d i n a 1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t c c d = 2 b a n k n c o l a d d r b c o l a d d r b d i n b 2 d i n b 3 d i n b 5 d i n b 4 d i n b 1 d i n b 0 d i n b 6 d i n b 7 d i n a 2 d i n a 3 d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 38 - 7.4.7.1 burst write t runcated by bst: wl = 1, bl = 16 note s : 1. the bst command truncates an ongoing write burst wl * t ck + t dqss after the rising edge of the clock where the burst terminate command is issued . 2. for lpddr2 - s4 devices, bst can only be issued a t even number of clock cycles after the write command . 3. additional bst commands are not allowed after t 4 and may not be issued until after the next read or write command . 7.4.7.2 burst read t runcated by bst: rl = 3, bl = 16 note s : 1. the bst command truncates an ongoing read burst rl * t ck + t dqsck + t dqsq after the rising edge of the clock where the burst terminate command is issued . 2. for lpddr2 - s4 devices, bst can only be issued a t even number of clock cycles after the read command . 3. additional bst commands are not allowed after t 4 and may not be issued until after the next read or write command. c a 0 - 9 [ c m d ] n o p b s t n o p n o p n o p n o p n o p n o p w r i t e d q s w l = 1 b a n k m c o l a d d r a c o l a d d r a d i n a 0 d i n a 1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 w l * t c k + t d q s s c k _ t / c k _ c d q s _ c d q s _ t d i n a 2 d i n a 3 d i n a 4 d i n a 5 d i n a 6 d i n a 7 b s t n o t a l l o w e d c a 0 - 9 [ c m d ] n o p b s t n o p n o p n o p n o p n o p n o p r e a d d q s r l = 3 b a n k n c o l a d d r a c o l a d d r a t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 r l * t c k + t d q s c k + t d q s q c k _ t / c k _ c d q s _ c d q s _ t d o u t a 2 d o u t a 1 d o u t a 0 d o u t a 3 d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 b s t n o t a l l o w e d
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 39 - 7.4.8 write d ata m ask one write data mask (dm) pin for each data byte (dq) will be supported on lpddr2 devices, consistent with the implementation on lpddr sdrams. each data mask (dm) may mask its respective data byte (dq) for any given cycle of the burst. data mask has identical timings on write operations as the data bits, though used as input o nly, is internally loaded identically to data bits to insure matched system timing . see 7 .4.14.2 precharge & auto precharge c larification table for write to precharge timings . 7.4.8.1 write d ata m ask timing d a t a m a s k t i m i n g t d h t d s t d s t d h v i h ( a c ) v i l ( a c ) v i h ( d c ) v i l ( d c ) v i h ( a c ) v i l ( a c ) v i h ( d c ) v i l ( d c ) [ c m d ] d q d m w l = 2 w i r t e t d q s s m i n t d q s s m a x t w r t w t r 0 1 2 3 0 1 2 3 c a s e 2 : m a x t d q s s c a s e 1 : m i n t d q s s d a t a m a s k f u n c t i o n , w l = 2 , b l = 4 s h o w n , s e c o n d d q m a s k e d d m d q d q d m d q s _ c d q s _ t c k _ c c k _ t d q s _ c d q s _ t d q s _ c d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 40 - 7.4.9 precharge o peration the precharge command is used to precharge or close a bank that has been activated. the precharge command is initiated by having cs_n low, ca0 high, ca1 high, ca2 low, and ca3 high at the rising edge of the clock. the precharge command can be used to prech arge each bank independently or all banks simultaneously. for 8 - bank devices, the ab flag, and the bank address bits, ba0, ba1, and ba2 are used to determine which bank(s) to precharge. the bank(s) will be available for a subsequent row access t rpab after an all - bank precharge command is issued and t rppb after a single - bank precharge command is issued. in order to ensure that 8 - bank devices do not exceed the instantaneous current supplying capability of 4 - bank devices, the row precharge time (t rp ) for an a ll - bank precharge for 8 - bank devices (t rpab ) will be longer than the row precharge time for a single - bank precharge (t rppb ) . 7.4.9.1 bank s election for precharge by a ddress b its ab (ca4r) ba 2 (ca 9 r) ba1 (ca8r) ba0 (ca7r) precharged bank(s) 8 - bank device 0 0 0 0 bank 0 only 0 0 0 1 bank 1 only 0 0 1 0 bank 2 only 0 0 1 1 bank 3 only 0 1 0 0 bank 4 only 0 1 0 1 bank 5 only 0 1 1 0 bank 6 only 0 1 1 1 bank 7 only 1 dont care dont care dont care all banks 7.4.10 burst read o peration f ollowed by precharge for the earliest possible precharge, the precharge command may be issued bl/2 clock cycles after a read command. for an untruncated burst, bl is the value from the mode register. for a truncated burst, bl is the effective burst length. a new bank active (comma nd) may be issued to the same bank after the row precharge time (t rp ). a precharge command cannot be issued until after t ras is satisfied. for lpddr2 - s4 devices, the minimum read to precharge spacing has also to satisfy a minimum analog time from the risi ng clock edge that initiates the last 4 - bit prefetch of a read command. this time is called t rtp (read to precharge). for lpddr2 - s4 devices, t rtp begins bl/2 - 2 clock cycles after the read command. if the burst is truncated by a bst command or a re ad command to a different bank , the effective bl shall be used to calculate when t rtp begins . see 7 .4.14.2 precharge & auto precharge c larification table for read to precharge timings .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 41 - 7.4.10.1 burst r ead f ollowed by precharge: rl = 3, bl = 8, ru(t rtp(min) /t ck ) = 2 7.4.10.2 burst r ead f ollowed by precharge: rl = 3, bl = 4 , ru(t rtp(min) /t ck ) = 3 c a 0 - 9 [ c m d ] n o p n o p n o p p r e c h a r g e n o p n o p a c t i v a t e n o p r e a d d q s r l = 3 b a n k m c o l a d d r a c o l a d d r a d o u t a 0 d o u t a 1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 d o u t a 2 d o u t a 3 d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 b a n k m b a n k m r o w a d d r r o w a d d r b l / 2 t r t p t r p c k _ t / c k _ c d q s _ c d q s _ t c a 0 - 9 [ c m d ] n o p n o p n o p p r e c h a r g e n o p n o p a c t i v a t e n o p r e a d d q s r l = 3 b a n k m c o l a d d r a c o l a d d r a d o u t a 0 d o u t a 1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 d o u t a 2 d o u t a 3 b a n k m b a n k m r o w a d d r r o w a d d r b l / 2 t r t p = 3 t r p c k _ t / c k _ c d q s _ c d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 42 - 7.4.11 burst write f ollowed by precharge for write cycles, a delay must be satisfied from the time of the last valid burst input data until the precharge command may be issued. this delay is known as the write r ecovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command to the same bank should be issued prior to the t wr delay. lpddr2 - s4 devices write data to the array in prefetch quadruples (prefetch = 4). the beginning of an internal write operation may only begin after a prefetch group has been latched completely . therefore, the write recovery time (t wr ) starts at different boundaries. the minimum write to precharge command spacing to the same bank is wl + bl/2 + 1 + ru(t wr /t ck ) clock cycles. for an untruncated burst, bl is the value from the mode register. for a truncated burst, bl is the effective burst length. see 7 .4.14.2 precharge & auto precharge c larification table for write to precharge timings . 7.4.11.1 burst w rite f ollwed by p recharge: wl = 1, bl = 4 c a 0 - 9 [ c m d ] d q s d q s t 0 t 1 t 2 t 3 t 4 t x t x + 1 t y t y + 1 > = t r p t w r t w r b a n k a c o l a d d r c o l a d d r b a n k a r o w a d d r b a n k a r o w a d d r n o p n o p n o p n o p n o p n o p p r e c h a r g e a c t i v a t e d i n a 0 d i n a 1 d i n a 2 d i n a 3 d i n a 0 d i n a 1 d i n a 2 d i n a 3 t d q s s m a x t d q s s m i n c o m p l e t i o n o f b u r s t w r i t e c a s e 1 : w i t h t d q s s ( m a x ) c a s e 2 : w i t h t d q s s ( m i n ) w l = 1 w l = 1 w r i t e c k _ t / c k _ c d q s _ c d q s _ t d q s _ c d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 43 - 7.4.12 auto precharge o peration before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto - precharge function. when a read or a write command is given to the lpddr2 sdram, the ap bit (ca0f) may be set to allow the active bank to automatically begin p recharge at the earliest possible moment during the burst read or write cycle. if ap is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst. if ap is high when the read or write command is issued, then the auto - precharge function is engaged. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon read or write latency) thus improving s ystem performance for random data access . 7.4.13 burst read with auto - precharge if ap (ca0f) is high when a read command is issued, the read with auto - precharge function is engaged. lpddr2 - s4 devices start an auto - precharge operation on the rising edge of the c lock bl/2 or bl/2 - 2 + ru(t rtp /t ck ) clock cycles later than the read with ap command , whichever is greater. refer to section 7 .4.14.2 precharge & auto precharge c larification table for equations related to auto - precharge for lpddr2 - s4. a new bank activate command may be issued to the same bank if both of the following two conditions are satisfied simultaneously. the ras precharge time (t rp ) has been satisfied from the clock at w hich the auto precharge begins. the ras cycle time (t rc ) from the previous bank activation has been satisfied . 7.4.13.1 burst r ead with auto - precharge: rl = 3, bl = 4, ru (trtp(min) /t ck ) = 2 c a 0 - 9 [ c m d ] n o p n o p n o p n o p n o p n o p a c t i v a t e n o p r e a d d q s r l = 3 b a n k m c o l a d d r a c o l a d d r a d o u t a 0 d o u t a 1 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 d o u t a 2 d o u t a 3 b a n k m r o w a d d r r o w a d d r b l / 2 t r t p > = t r p p b c k _ t / c k _ c d q s _ c d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 44 - 7.4.14 burst w rite with auto - precharge if ap (ca0f) is high when a write command is issued, the write with auto - precharge function is engaged. the lpddr2 sdram starts an auto precharge operation on the rising edge which is t wr cycles after the completion of the burst write. a new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied. the ras precharge time (t rp ) has been satisfied from the clock at w hich the auto precharge begin s. the ras cycle time (t rc ) from the previous bank activation has been satisfied. 7.4.14.1 burst w rite with auto - precharge : wl = 1, bl = 4 c a 0 - 9 [ c m d ] d q s t 0 t 1 t 2 t 3 t 4 t r p p b t w r b a n k a c o l a d d r c o l a d d r b a n k a r o w a d d r r o w a d d r n o p n o p n o p n o p n o p a c t i v a t e d i n a 0 d i n a 1 d i n a 2 d i n a 3 w l = 1 w r i t e t 5 t 6 t 7 t 8 n o p n o p c k _ t / c k _ c d q s _ c d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 45 - 7.4.14.2 precharge & auto precharge c larification fr o m command t o com m an d minim u m delay b e twe e n f r om c om m and to t o c omm a nd unit note s read prech a r g e (to same ba n k as re a d ) bl/2 + max(2, ru(t rtp /t ck )) - 2 clk 1 prec h arge a ll bl/2 + max(2, ru(t rtp /t ck )) - 2 clk 1 bst (for reads) precharge (to same bank as read) 1 clk 1 precharge a ll 1 clk 1 r e ad w/ap prec h arg e (t o s a m e b a nk as r e a d w/ap ) bl/2 + max(2, ru(t rtp /t ck )) - 2 clk 1 , 2 prec h arge a ll bl/2 + max(2, ru(t rtp /t ck )) - 2 clk 1 activat e (to sa m e bank as rea d w/a p) bl/2 + max(2, ru(t rtp /t ck )) - 2 + ru(t rppb /t ck ) clk 1 write or write w/ap (same bank) lllegal clk 3 write or write w/ap (different bank) rl + bl/2 + ru(t dqsckmax /t ck ) - wl + 1 clk 3 read or read w/ap (same bank) lllegal clk 3 read or read w/ap (different bank) bl/2 clk 3 write pr ec h a r g e ( t o sa m e ba nk as w r i t e) wl + bl/2 + ru(t wr /t ck ) + 1 clk 1 prec h arge a ll wl + bl/2 + ru(t wr /t ck ) + 1 clk 1 bst (for writes) precharge (to same bank as write) wl + ru(t wr /t ck ) + 1 clk 1 precharge a ll wl + ru(t wr /t ck ) + 1 clk 1 write w/ap pr e charg e (to same bank as write w/ap ) wl + bl/2+ ru(t wr /t ck ) + 1 clk 1 prec h arge a ll wl + bl/2 + ru(t wr /t ck ) + 1 clk 1 activ a t e (to same b a nk a s wr ite w/ap) wl + bl/2 + ru(t wr / t ck ) + 1 + ru(t rppb /t ck ) clk 1 write or write w/ap (same bank) lllegal clk 3 write or write w/ap (different bank) bl/2 clk 3 read or read w/ap (same bank) lllegal clk 3 read or read w/ap (different bank) wl + bl/2 + ru(t wtr /t ck ) + 1 clk 3 precharge pr e charg e (to same b a nk a s prec h arge ) 1 clk 1 prec h arge a ll 1 clk 1 prec h arge al l precharge 1 clk 1 prec h arge a ll 1 clk 1 note s : 1. for a given bank, the precharge period should be counted from the latest precharge command, either one bank p recharge or p recharge all, issued to that bank. the precharge period is satisfied after t rp depending on the latest precharge command issued to that bank . 2. any command issued during the specified minimum delay time is illegal . 3. after read with ap, seamless read operations to different banks are supported. after write with ap, seamless write operat ions to different banks are supported. read w/ap and write w/ap may not be interrupted or truncated .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 46 - 7.4.15 refresh c ommand the refresh command is initiated by having cs_n low, ca0 low, ca1 low, and ca2 high at the rising edge of clock. per bank refresh is initiated by having ca3 low at the rising edge of clock and all bank refresh is initiated by having ca3 hi gh at the rising edge of clock. per bank refresh is only allowed in devices with 8 banks. a per bank refresh command, refpb performs a refresh operat ion to the bank which is scheduled by the bank counter in the memory device. the bank sequence of per bank refresh is fixed t o be a sequential round - robin: 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 - ... . the bank count is synchronized between the controller and the sdram upon issuing a reset command or at every exit from self refresh, by resetting bank count to zero. the bank addressing for the per bank refresh count is the same as established in the sing le - bank precharge command (s ee 7.4.9.1 bank s election for precharge by a ddress b its table ) . a bank must be idle before it can be refreshed. it is t he responsibility of the controller to track the bank being refreshed by the per bank refresh command . as shown in 7.4.15.1 command scheduling separations r elated to refresh table , the ref p b command may not be issued to the memory until the following conditions have been met: a) t he t rfcab has been satisified after the prior refab command b) t he t rfc p b has been satisi fied after the prior ref p b command c) t he t rp has been satisified after prior precharge commands to that given bank t he t rrd has been satisfied after the prior activate command (if applicable, for example after activating a row in a different bank than affected by the refpb command) . the target bank is inaccessable during the per bank refresh cycle time (t rfcpb ), however other banks within the device are accessable and may be addressed during the per bank refresh cycle. during the refpb operation, any of the banks other than the one being refreshed can be maintained in active state or accessed by a read or a write command . whe n the per bank refresh cycle has completed, the affected bank will be in the idle state . as shown in 7.4.15.1 command scheduling separations r elated to refresh table , after issuing ref p b: a) t he t rfc p b must be satisified before issuing a refab command b) t he t rfc p b must be satisfied before issuing an activate command to the same bank c) the t rrd must be satisified before issuing an activate command to a different bank d) the t rfcpb must be satisified before issuing another refpb command an all bank refresh command, refab performs a refresh operation to all banks. all banks have to be in idle state when refab is issued (for instance, by precharge all - bank command). refab also synchronizes the bank count between the controller and the sdram to zero. as shown in 7.4.15.1 command scheduling separations r elated to refresh table , the refab command may not be issued to the memory until the following conditions have been met: a) t he t rfcab has been satisified after the prior refab command b) the t rfcpb has been satisified after the prior refpb command c) t he t rp has been satisified after prior precharge commands when the all bank refresh cycle has completed, all banks will be in the idle state. as shown in 7.4.15.1 command scheduling separations r elated to refresh table , after issuing refab: a) t he t rfcab latency must be satisfied before issuing an activate command b) t he t rfcab latency must be satisfied before issuing a refab or refpb command
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 47 - 7.4.15.1 command scheduling separations r elated to refresh symbol minimum delay from to note t rfcab refab refab activate cmd to any bank ref p b t rfc p b ref p b refab activate cmd to same bank as ref pb ref p b t rrd ref pb activate cmd to different bank than ref pb activate refpb affecting an idle bank (different bank than activate) 1 activate cmd to different bank than prior activate note: 1. a bank must be in the idle state before it is refreshed. therefore, after activate, refab is not allowed and refpb is allowed only if it affects a bank which is in the idle state . 7.4.16 lpddr2 sdram refresh requirements (1) minimum number of refresh commands: the lpddr2 sdram requires a minimum number of r refresh (refab) commands within any rolling refresh window (t refw = 32 ms @ mr4[2:0] = 011 or t case 85 c ). the r equired minimum number of refresh commands and resulting average refresh interval (t ref i ) are given in 8 .6 .1 refresh requirement parameters table . see mode register 4 for t refw and t refi refresh multipliers at different mr4 settings. (2) burst refresh limitation: to limit maximum current consumption, a maximum of 8 refab commands may be issued in any rolling t refbw (t refbw = 4 x 8 x t rfcab ). this condition does not apply if refpb commands are used. (3) refresh requirements and self - refresh: if any time within a refresh window is spent in self - refresh mode, the number of required refresh commands in this particular window is reduced to: r* = r - ru{t srf / t refi } = r - ru{r * t srf / t refw } ; where ru stands for the round - up function .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 48 - 7.4.16.1 definition of t srf several examples on how t srf is caclulated: a: with the time spent in self - refresh mode fully enclosed in the refresh window (t re fw ) . b: at self - refresh entry . c: at self - refresh exit . d: with several different invervals spent i n self refresh during one t refw interval . a ) c k e c k e c k e c k e b ) c ) d ) t r e f w t s r f e n t e r s e l f - r e f r e s h e x i t s e l f - r e f r e s h e x i t s e l f - r e f r e s h e n t e r s e l f - r e f r e s h e n t e r s e l f - r e f r e s h e x i t s e l f - r e f r e s h e x i t s e l f - r e f r e s h t r e f w t s r f t s r f t s r f 1 t s r f 2 t r e f w t r e f w t s r f = t s r f 1 + t s r f 2
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 49 - in contrast to jesd79 and jesd79 - 2 and jesd79 - 3 compliant sdram devices, lpddr2 - s4 devices allow significant flexibiliy in scheduling refresh comm a nds, as long as the boundary conditions above are met. in the mos t straight forward case a refresh command should be scheduled every t refi . in this case self - refresh may be entered at any time. the users may choose to deviate from this regular refresh pattern e.g., to enable a period where no refreshes are required. as an example, using a 1gb lpddr2 - s4 device, the user can choose to issue a refresh burst of 4096 refresh commands with the maximum allowable rate (limited by t refbw ) followed by a long time without any refresh commands, until the refresh window is complete, then repeating this sequence. the achieveable time without refresh commands is given by t refw - (r / 8) * t refbw = t refw - r * 4 * t rfcab .@ t case 85 c this can be up to 32 ms - 4096 * 4 * 130 ns 30 ms . while both - the regular and the burst/pause - p atterns can satisfy the refresh requirements per rolling refresh interval, if they are repeated in every subsequent 32 ms window, extreme care must be taken when transitioning from one pattern to another to satisfy the refresh requirement in every rolling refresh window during the transition. figure of 7.4.16.3 shows an example of an allowable transition from a burst pattern to a regular, distributed pattern. if this transition happens directly after the burst refresh phase, all rolling t refw in terval will have at least the required number of refreshes. figure of 7.4.16.4 shows an example of a non - allowable transition . in this case the regular refresh pattern starts after the completion of the pause - phase of the burst/pause refresh pattern. for several rolling t refw intervals the minimmun number of ref resh commands is not satisfied. the understanding of the pattern transition is extremly relevant (even if in normal operation only one pattern is employed), as in self - refresh - mode a regular, distributed refresh pattern has to be assumed, which is reflected in the equation for r* above. therefore it is recommended to enter self - refresh - mode only directly after the burst - phase of a burst/pause refresh patte rn as indicated in f igure of 7.4.16.5 a nd begin with the burst phase upon exit from self - refresh.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 50 - 7.4.16.2 regular, distributed refresh pattern note s : 1. compared to repetitive burst refresh with subsequent refresh p ause. 2. for an example, in a 1gb lpddr2 device at t case 85 c , the distributed refresh pattern would have one refresh command per 7.8 s ; the burst refresh pattern would have an average of one refresh command per 0. 52 s followed by 3 0 ms without any refresh command . 7.4.16.3 allowable transition from repetitive burst refresh note s : 1. shown with subsequent refresh pause to regular distributed refresh pattern . 2. for an example, in a 1gb lpddr2 device at t case 85 c , the distributed refresh pattern would have one refresh command per 7.8 s ; the burst refresh pattern would have an average of one refresh command per 0. 52 s followed by 3 0 ms without any refresh command . t r e f i t r e f i t r e f b w t r e f b w 0 m s 4 , 0 9 6 3 2 m s 6 4 m s 9 6 m s 8 , 1 9 2 4 , 0 9 6 4 , 0 9 7 8 , 1 9 2 8 , 1 9 3 1 2 , 2 8 8 1 2 , 2 8 9 1 6 , 3 8 4 1 2 , 2 8 8 t r e f i t r e f i t r e f b w t r e f b w 0 m s 3 2 m s 6 4 m s 9 6 m s 4 , 0 9 6 4 , 0 9 7 8 , 1 9 2 1 2 , 2 8 8 1 0 , 2 4 0 1 6 , 3 8 4
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 51 - 7.4.16.4 not - allowable transition from repetitive burst refresh note s : 1. shown with subsequent refresh pause to regular distributed refresh pattern . 2. only 2048 refresh commands (< r which is 4096 ) in the indicated t refw window. 7.4.16.5 recommended self - r efresh e ntry and e xit note: 1. in conjunction with a b urst/ p ause refresh pattern s . t r e f i t r e f i t r e f b w t r e f b w 0 m s 3 2 m s 6 4 m s 9 6 m s 4 , 0 9 6 4 , 0 9 7 8 , 1 9 2 1 0 , 2 4 0 1 2 , 2 8 8 8 , 1 9 3 t r e f w = 3 2 m s n o t e n o u g h r e f r e s h c o m m a n d s i n t h i s r e f r e s h w i n d o w ! ! t r e f b w t r e f b w 0 m s 3 2 m s 4 , 0 9 6 4 , 0 9 7 8 , 1 9 2 s e l f - r e f r e s h
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 52 - 7.4.16.6 all bank refresh operation 7.4.16.7 per bank refresh operation note s : 1. in the beginning of this example, the refpb bank is pointing to bank 0 . 2. operations to other banks than the bank being refreshed are allowed during the t rfcpb period . t 0 > = t r p a b p r e c h a r g e n o p n o p r e f a b a n y c a 0 - 9 [ c m d ] a b c k _ t / c k _ c t 1 t 2 t 3 t 4 t x t x + 1 t y t y + 1 n o p n o p r e f a b > = t r f c a b > = t r f c a b c a 0 - 9 [ c m d ] c k _ t / c k _ c t 0 t 1 t x t x + 1 t x + 2 t y t y + 1 t z t z + 1 > = t r p a b > = t r f c p b > = t r f c p b a c t i v a t e c o m m a n d t o b a n k 1 r e f r e s h t o b a n k 1 r e f r e s h t o b a n k 0 a c t a b r o w a b a n k 1 r o w a r e f p b r e f p b n o p n o p p r e c h a r g e
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 53 - 7.4.17 self refresh o peration the self refresh command can be used to retain data in the lpddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the lpddr2 sdram retains data without external clocking. the lpddr2 sdram device has a built - in timer to accommodate self refresh operation. the self refresh command is defined by having cke low, cs_n low, ca0 low, ca1 low, and ca2 high at the rising edge of the clock. cke must be high during the previous clock cycle. a nop command must be driven in the clock cycle following the power - down command. once the command is registered , cke must be held low to keep the device in self refresh mode. lpddr2 - s4 devices can operate in self refresh in both the standard or extended temperature ranges. lpddr2 - s4 devices will also manage self refresh power consumption when the operating tempera ture changes, lower at low temperatures and higher temperatures. once the lpddr2 sdram has entered self refresh mode, all of the external signals except cke, are dont care. for proper self refresh operation, power supply pin s (v dd1 , v dd2 , and v ddca ) mu st be at valid levels. v ddq may be turned off during self - refresh. prior to exiting self - refresh, v ddq must be within specified limits . v refdq and v refca may be at any level within minimum and maximum levels (see section 8 .1 absolute maximum dc ratings table ) . h owever prior to exit self - refresh, v refdq and v refca must be within specified limits ( s ee section 8 .2.1.1 recommended dc operating conditions table ) . the sdram initiates a minimum of one all - bank refresh command internally within t ckesr period once it enters self refresh mode. the clock is internally disabled during self refresh operation to save power. the minimum time that the lpddr2 sdram must remain in self refresh mode is t ckesr . the user may change the external clock frequency or halt the external clock one clock after self refresh entry is registered; however, the clock must be restarted and stable before the device can exit self refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock shall be stable and w ithin specified limits for a minmum of 2 clock cycles prior to cke going back high. once self refresh exit is registered, a delay of at least t xsr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in pro gress. cke must remain high for the entire self refresh exit period t xsr for proper operation except for self refresh re - entry. nop commands must be registered on each positive clock edge during the self refresh exit interval t xsr . the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, it is required that at least one refresh command ( 8 per - bank or 1 all - bank) is issued bef ore entry into a subsequent self refresh .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 54 - for lpddr2 sdram, the maximum duration in power - down mode is only limited by the refresh requirements outlined in section 7 .4.16 lpddr2 sdram refresh requirements , since no refresh operations are performed in power - down mode. figure of self refresh operation note s : 1. input clock frequency may be changed or stopped during self - refresh, provided that upon exiting self - refresh, a minimum of 2 clocks of stable clock are provided and the clock frequency is between the minimum and maximum frequency for the particular speed g rad 2. device must be in the all banks idle state prior to entering self refresh mode . 3. t xsr begins at the rising edge of the clock after cke is driven high . 4. a valid command may be issued only after t xsr is satisfied. nops shall be issued during t xsr . 7.4.18 partial array self - refresh: bank masking each bank of lpddr2 sdram can be independently configured whether a self refresh operation is taking place. one mode register unit of 8 bits accessible via mrw command is assigned to program the bank masking status of each bank up to 8 banks. for bank masking bit assignments, see section 7 . 3.13 mode register 16 mr16_pasr_bank mask (ma[7:0] = 10h) . the mask bit to the bank controls a refresh operation of entire memory within the bank. if a bank is masked via mrw, a refresh operation to the entire bank is blocked and data retention by a bank is not guaranteed in self refresh mode. to enable a refresh operation to a bank, a coupled mask bit has to be programmed, unmasked. when a bank mask bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask bits . 7.4.19 partial array self - refresh: segment masking segment masking scheme may be used in place of or in combination with bank masking scheme in lpddr2 - s4 sdram. the number of segments differ by the density and the setting of each segment mask bit is applied across all the banks. for segment masking bit a ss ignments, see s ection 7.3.14 mode register 17 mr17_pasr_segment mask (ma[7:0] = 11h) . for those refresh - enabled banks, a refresh operation to the ad dress range which is represented by a segment is blocked when the mask bit to this segment is programmed, masked. programming of segment mask bits is similar to the one of bank mask bits . 2 t c k ( m i n ) t i h c k e t c k e s r ( m i n ) t i s c k e t i h c k e v a l i d e n t e r s r n o p n o p n o p v a l i d e x i t s r i n p u t c l o c k f r e q u e n c y m a y b e c h a n g e d o r s t o p p e d d u r i n g s e l f - r e f r e s h e n t e r s e l f - r e f r e s h e x i t s e l f - r e f r e s h t x s r ( m i n ) t i s c k e c k e [ c m d ] c k _ c c k _ t c s _ n
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 55 - table of example of bank and segment masking use in lpddr2 - s4 dev ices segment mask(mr17) bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank mask (mr16) 0 1 0 0 0 0 0 1 segment 0 0 - m - - - - - m segment 1 0 - m - - - - - m segment 2 1 m m m m m m m m segment 3 0 - m - - - - - m segment 4 0 - m - - - - - m segment 5 0 - m - - - - - m se gment 6 0 - m - - - - - m segment 7 1 m m m m m m m m note: this table illustrates an example of an 8 - bank lpddr2 - s4 device, when a refresh operation to bank 1 and bank 7, as well as segment 2 and segment 7 are masked 7.4.20 mode register read command the mode register read command is used to read configuration and statu s data from mode registers. the mode register read (mrr) command is initiated by having cs_n low, ca0 low, ca1 low, ca2 low, and ca3 high at the rising edge of the clock. the mode register is selected by {ca1f - ca0f, ca9r - ca4r}. the mode register contents are available on the first data beat of dq [ 0 : 7 ] , rl * t ck + t dqsck + t dqsq after the rising edge of the clock where the mode register read command is issued. subsequent data b ea ts contai n valid, but undefined content , except in the case of the dq calibrati on function dqc, where subsequent data beats contain valid content as described in section 7.4.21.2 dq calibration . all dqs_t, dqs_c shall be toggled for the duration of the mode register read burst. the mrr command has a burst length of four. the mode register read operation (consisting of the mrr command and the corresponding data traffic) shall not be interrupted. the mrr command period (t mrr ) is 2 clock cycles. mode register reads to reserved and write - only registers shall return valid, but undefined content on all data beats and dqs_t, dqs_c shall be toggled .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 56 - 7.4.20.1 mode register read t iming e xample: rl = 3, t mrr = 2 note s : 1. mode register read has a burst length of fou r. 2. mode register read operation shall not be interrupted . 3. mode register data is valid only on dq[0 - 7] on the first beat. subsequent beats contain valid, but undefined data. dq[8 - max] contain valid, but undefined data for the duration of the mrr burst . 4. the mode register command period is t mrr . no command (other than nop) is allowed during this period. 5. mode register reads to dq calibration registers mr32 and mr40 are described in the section on dq calibration . 6. minimum mode register read to write latency is rl + ru(t dqsckmax /t ck ) + 4/2 + 1 - wl clock cycles. 7. minimum mode register read to mode register write latency is rl + ru(t dqsckmax /t ck ) + 4/2 + 1 clock cycles. the mrr command shall not be issued earlier than bl/2 clock cycles after a prior read command and wl + 1 + bl/2 + ru( t wtr /t ck ) clock cycles after a prior write command, because read - bursts and write - bursts shall not be truncated by mrr. note that if a read or write burst is truncated with a burst termi nate (bst) command, the effective burst length of the truncated burst should be used as bl . c m d n o t a l l o w e d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 c a 0 - 9 [ c m d ] d q [ 0 - 7 ] d q [ 8 - m a x ] t m r r = 2 t m r r = 2 r l = 3 r e g a r e g a r e g b r e g b m r r m r r d o u t a u n d e f d o u t b u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f c k _ t / c k _ c d q s _ t d q s _ c
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 57 - 7.4.20.2 read to mrr t iming e xample: rl = 3, t mrr = 2 note s : 1. the minimum number of clocks from the burst read command to the mode register read command is bl/2. 2. the mode register read command period is t mrr . no command (other than nop) is allowed during this period . 7.4.20.3 burst write followed by mrr: rl = 3, wl = 1, bl = 4 note s : 1. the minimum number of clock cycles from the burst write command to the mode register read command is [wl + 1 + bl/2 + ru( t wtr /t ck )] . 2. the mode register read command period is tmrr. no command (other than nop) is allowed during this period . c m d n o t a l l o w e d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 c a 0 - 9 [ c m d ] d q [ 0 - 7 ] d q [ 8 - m a x ] b l / 2 t m r r = 2 r l = 3 b a m c o l a d d r a r e g b r e g b r e a d m r r d o u t a 0 d o u t b u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f u n d e f c o l a d d r a d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 c k _ t / c k _ c d q s _ c d q s _ t t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 c a 0 - 9 [ c m d ] b a n c o l a d d r a r e g b r e g b w r i t e m r r c o l a d d r a d i n a 0 d i n a 1 d i n a 2 d i n a 3 c m d n o t a l l o w e d w l = 1 t w t r r l = 3 t m r r = 2 c k _ t / c k _ c d q s _ c d q s _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 58 - 7.4.21 temperature sensor lpddr2 sdram features a temperature sensor whose status can be read from mr4. this sensor can be used to determine an appropriate refresh rate, determine whether ac timing derating is required in the extended temperature range and/or monitor the operating temperature. either the temperature sensor or the device operating temperature (s ee 8 .2.3 operating temperature conditions table ) may be used to determine whether operating temperature requirements are being met. lpddr2 devices shall monitor device temperature and update mr4 according to t tsi . upon exiting self - refresh or power - down, the device temperature status bi ts shall be no older than t tsi . when using the temperature sensor, the actual device case temperature may be higher than the operating temperature specification (s ee 8 .2.3 operating temperature conditions ta ble ) that applies for the standard or extended temperature ranges. for example, t case may be above 8 5 c when mr4[2:0] equals 011 b . to assure proper operation using the temperature sensor, applications should consider the following factors: tempgradient i s the maximum temperature gradient experienced by the memory device at the temperature of interest over a range of 2 c . readinterval is the time period between mr4 reads from the system. tempsensorinterval (t tsi ) is maximum delay between internal updates of mr4. sysrespdelay is the maximum time between a read of mr4 and the response by the system. lpddr2 devices shall allow for a 2 c temperature margin between the point at which the device temperature enters the extended temperature range and point at w hich the controller re - configures the system accordingly. in order to determine the required frequency of polling mr4, the system shall use the maximum tempgradient and the maximum response time of the system using the following equation: tempgradient x ( readinterval + t tsi + sysrespdelay ) 2 c table of temperature sensor symbol parameter max/min value unit tempgradient system temperature gradient max system dependent c / s readinterval mr4 read interval max system dependent ms t tsi temperature sensor interval max 32 ms sysrespdelay system response delay max system dependent ms tempmargin device temperature margin max 2 oc for example, if tempgradient is 10 c /s and the sysrespdelay is 1 ms : 10 c / s x ( readinterval + 32 ms + 1 ms ) 2 c i n this case, readinterval shall be no greater than 167 ms .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 59 - 7.4.21.1 t emperature sensor timing 7.4.21.2 dq calibration lpddr2 device feature s a dq calibration function that outputs one of two predefined system timing calibration patterns. a mod e register read to mr32 (pattern a) or mr40 (pattern b) will return the specified pattern on d q [ 0 ] a n d d q [ 8 ] f o r x 1 6 d e v i c e s , a n d d q [ 0 ] , d q [ 8 ] , d q [ 1 6 ] , a n d d q [ 2 4 ] f o r x 3 2 d e v i c e s . for x16 devices, dq[7:1] and dq[15:9] may optionally drive the same inf ormation as dq[0] or may drive 0b during the mrr burst. for x32 devices, dq[7:1], dq[15:9], dq[23:17], and dq[31:25] may optionally drive the same information as dq[0] or may drive 0b during the mrr burst. for lpddr2 - s 4 devices, mrr dq calibration command s may only occur in the idle state. table of data calibration pattern description pattern mr# bit time 0 bit time 1 bit time 2 bit time 3 description pattern a mr32 1 0 1 0 read to mr32 return dq calibration pattern a pattern b mr40 0 0 1 1 read to mr40 return dq calibration pattern b t e m p d e v i c e t e m p m a r g i n m r 4 t r i p l e v e l t e m p e r a t u r e s e n s o r u p d a t e h o s t m r 4 r e a d m r r m r 4 = 0 x 0 3 m r 4 = 0 x 0 3 m r 4 = 0 x 8 6 m r 4 = 0 x 8 6 m r 4 = 0 x 8 6 m r 4 = 0 x 8 6 m r 4 = 0 x 0 6 r e a d l n t e r v a l m r r m r 4 = 0 x 8 6 t t s i t i m e s y s r e s p d e l a y 2 c < ( t t s i + r e a d l n t e r v a l + s y s r e s p d e l a y ) t e m p g r a d i e n t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 60 - 7.4.21.3 mr32 and mr40 dq calibration t iming e xample: rl = 3, t mrr = 2 note s : 1. mode register read has a burst length of four. 2. mode register read operation shall not be interrupted . 3. mode register reads to mr32 and mr40 drive valid data on dq[0] during the entire burst. for x16 devices, dq[8] shall drive the same information as dq[0] during the burst. for x32 devices, dq[8], dq[16], and dq[24] shall drive the same information as dq[0] during the burst. 4. fo r x16 devices, dq[7:1] and dq[15:9] may optionally drive the same information as dq[0] or they may drive 0b during the burst. for x32 devices, dq[7:1], dq[15:9], dq[23:17], and dq[31:25] may optionally drive the same information as dq[0] or they may drive 0b during the burst. 5. the mode register command period is tmrr. no command (other than nop) is allowed during this period . c k _ t / c k _ c c a 0 - 9 [ c m d ] d q s _ t d q s _ c d q [ 0 ] d q [ 7 : 1 ] d q [ 8 ] d q [ 1 6 ] d q [ 2 4 ] d q [ 1 5 : 9 ] d q [ 2 3 : 1 7 ] d q [ 3 1 : 2 5 ] t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 x 1 6 x 3 2 p a t t e r n a p a t t e r n b r l = 3 t m r r = 2 c m d n o t a l l o w e d o p t i o n a l l y d r i v e n t h e s a m e a s d q 0 o r t o 0 b r e g 3 2 r e g 3 2 r e g 4 0 r e g 4 0 m r r 4 0 m r r 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t m r r = 2
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 61 - 7.4.22 mode register write command the mode register write command is used to write configuration data to mode registers . the mode register write (mrw) command is initiated by having cs_n low, ca0 low, ca1 low, ca2 low, and ca3 low at the rising edge of the clock. the mode register is selected by {ca1f - ca0f, ca9r - ca4r}. the data to be written to the mode register is contained in ca9f - ca2f. th e mrw command period is defined by t mrw . mode register writes to read - only registers shall have no impact on the functionality of the device. for lpddr2 - s4 devices, the mrw may only be issued when all banks are in the idle precharge state. one method of e nsuring that the banks are in the idle precharge state is to issue a precharge - all command. 7.4.22.1 mode register write t iming e xample: rl = 3, t mrw = 5 note s : 1. the mode register write command period is t mrw . no command (other than nop ) is allowed during this period. 2. at time t y , the device is in the idle state . 7.4.22.2 truth table for mode register read (mrr) and mode register write (mrw) current state command intermediate state next state all banks idle mrr mode register reading (all banks idle) all banks idle mrw mode register writing (all banks idle) all banks idle mrw (reset) resetting (device auto - initialization ) all banks idle bank(s) active mrr mode register reading (bank(s) active ) bank(s) active mrw not allowed not allowed mrw (reset) not allowed not allowed c m d n o t a l l o w e d c a 0 - 9 [ c m d ] c k _ t / c k _ c t 2 t 1 t 0 t x t x + 1 t x + 2 t y + 1 t y + 2 t y m r w m r w a n y m r a d d r m r d a t a m r d a t a m r a d d r t m r w t m r w
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 62 - 7.4.23 mode register write reset (mrw reset) any mrw command issued to mrw63 initiates an mrw reset. the mrw reset command brings the device to the device auto - initialization (resetting) state in the power - on initialization sequence (see step 3 in section s 7 .2.1 power ramp and device initialization ) . the mrw reset command may be issued from the idle state for lpddr2 - s4 devices. this command resets all mode registers to their default values. no commands other than nop may be issued to t he lpddr2 device during the mrw reset period (t init4 ). after mrw reset, boot timings must be observed until the device initialization sequence is complete and the device is in the idle state. array data for lpddr2 - s4 devices are undefined after the mrw res et command. for the timing diagram related to mrw reset, refer to 7 .2.3 power ramp and initialization sequence figure . 7.4.24 mode register write zq calibration command the mrw command is also used to initiate the zq calibration command. the zq calibration command is used to calibrate the lpddr2 ouput drivers (ron) over process, temperature, and voltage. lpddr2 - s4 devices support zq calibration. there are four zq calibration commands and related timings times, t zqinit , t zqreset , t zqcl , and t zqcs . t zqinit corresponds to the initialization calibration, t z qreset for resetting zq setting to default, t zqcl is for long calibration, and t zqcs is for short calibratio n. see mode register 10 (mr10) for description on the command codes for the different zq calibration commands. the initialization zq calibration (zq init) shall be performed for lpddr2 - s4 devices. this initialization calibration achieves a ron accuracy of 15%. after initialization, the zq long calibration may be used to re - calibrate the system to a ron accuracy of 15%. a zq short calibration may be u sed periodically to compensate for temperature and voltage drift in the system. the zqreset command resets the ron calibration to a default accuracy of 30% across process, voltage, and temperature. this command is used to ensure ron accuracy to 30% when zqcs and zqcl are not used. one zqcs command can effectively correct a minimum of 1.5% (zqcorrection) of ron impedance error within t zqcs for all speed bins assuming the maximum sensitivities specified in the output driver voltage and temperature sensitiv ity. the appropriate interval between zqcs commands can be determined from these tables and other application - specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) d rift rates that the lpddr2 is subject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drondt) and vsens = max(drondv) define the lpddr2 temperature and voltage sensitivities. fo r example, if tsens = 0.75% / ? c , vsens = 0.20% / mv, tdriftrate = 1 ? c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as: = 0. 4 s for lpddr2 - s4 devices, a zq calibration comma nd may only be issued when the device is in idle state with all banks precharged. no other activities can be performed on the lpddr2 data bus during the calibration period (t zqinit , t zqcl , t zqcs ). the quiet time on the lpddr2 data bus helps to accurately calibrate ron. there is no required quiet time after the zq reset command. if multiple devices share a single zq resistor, only one device may be calibrating at any given time. after calibration is achieved, the lpddr2 device shall disable the zq pin s cur rent consumption path to reduce power. in systems that share the zq resistor between devices, the controller must not allow overlap of t zqinit , t zqcs , or t zqcl between the devices. zq reset overlap is allowed. if the zq resistor is absent from the system, zq shall be connected to v ddca . in this case, the lpddr2 device shall ignore zq calibration commands and the device will use the default calibration settings (see section 8 .2.6. 5 ron pu and ron pd characteristics without zq calibration output driver dc electrical characteristics without zq calibration table) . ) ( + ) ( vdriftrate vsens tdriftrate tsens on zqcorrecti 15) (0.20 + 1) (0.75 1.5
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 63 - 7.4.24.1 zq calibration initialization t iming e xample note s : 1. the zq calibration initialization period is t zqinit . no command (other than nop) is allowed during this period. 2. cke must be continuously registered high during the calibration period . 3. all devices connected to the dq bus should be high impedance during the calibra tion process. 7.4.24.2 zq calibration short t iming e xample note s : 1. the zq calibration short period is t zqcs . no command (other than nop) is allowed during this period. 2. cke must be continuously registered high during the calibration period . 3. all devices connected to the dq bus should be high impedance during the calibration process. c k _ t / c k _ c c a 0 - 9 [ c m d ] t 0 t 1 t 2 t 3 t 4 t 5 t x t x + 1 t x + 2 t z q i n i t c m d n o t a l l o w e d m r w a n y m r a d d r m r d a t a c k _ t / c k _ c c a 0 - 9 [ c m d ] t 0 t 1 t 2 t 3 t 4 t 5 t x t x + 1 t x + 2 t z q c s c m d n o t a l l o w e d m r w a n y m r a d d r m r d a t a
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 64 - 7.4.24.3 zq calibration long t iming e xample note s : 1. the zq calibration long period is t zqcl . no command (other than nop) is allowed during this period. 2. cke must be continuously registered high during the calibration period . 3. all devices connected to the dq bus should be high impedance during the calibration process. 7.4.24.4 zq calibration reset t iming e xample note s : 1. the zq calibration reset period is t zqreset . no command (other than nop) is allowed during this period. 2. cke must be continuously registered high during the calibration period . 3. all devices connected to the dq bus should be high impedance during the calibration process. c k _ t / c k _ c c a 0 - 9 [ c m d ] t 0 t 1 t 2 t 3 t 4 t 5 t x t x + 1 t x + 2 t z q c l c m d n o t a l l o w e d m r w a n y m r a d d r m r d a t a c k _ t / c k _ c c a 0 - 9 [ c m d ] t 0 t 1 t 2 t 3 t 4 t 5 t x t x + 1 t x + 2 t z q r e s e t c m d n o t a l l o w e d m r w a n y m r a d d r m r d a t a
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 65 - 7.4.24.5 zq external resistor value, tolerance, and capacitive loading to use the zq calibration function, a 240 ohm 1% tolerance external resistor must be connected between the zq pin and ground. a single resistor can be used for each lpddr2 device or one resistor can be shared between multiple lpddr2 devices if the zq calibration timings for each lpddr2 device do not overlap. the total capacitive loading on the zq pin must be limited (see section 8 .2. 6. 7 input/output capacitance table ) . 7.4.25 power - d own for lpddr2 sdram, power - down is synchronously entered when cke is registered low and cs_n high at the rising edge of clock. cke must be registered high in the previous clock cycle. a nop command must be driven in the clock cycle following the power - down command. cke is not allowed to go low while mode register, read, or write operation s are in progress. cke is allowed to go low while any of other ope rations such as row activation, preactive, precharge , autoprecharge, or refresh is in progress, but power - down i dd spec will not be applied un til finishing those operation s. timing diagrams are shown in the following pages with details for entry into power down. for lpddr2 sdram, if power - down occurs when all banks are idle, this mode is referred to as idle power - down; if power - down occurs when there is a row active in any bank, this mode is re ferred to as active power - down. entering power - down deactivates the input and output buffers, excluding ck_t, ck_c, and cke. in power - down mode, cke must be maintained low while all other input signals are dont care. cke low must be maintained until t cke has been satisfied. v ref must be maintained at a valid level during power down . v ddq may be turned off during power down. if v ddq is turned off, then v refdq must also be turned off. prior to exiting power down, both v ddq and v refdq must be within thei r respective min/max operating ranges ( s ee 8 .2.1.1 recommended dc operating conditions table ) . for lpddr2 sdram, the maximum duration in power - down mode is only limited by the refresh requirements outlined in section 7 .4.16 lpddr2 sdram refresh requirements , as no refresh operations are performe d in power - down mode. the power - down state is exited when cke is registered high. the controller shall drive cs_n high in conjunction with cke high when exiting the power - down state. cke high must be maintained until t cke has been satisfied. a valid, execu table command can be applied with power - down exit latency, t xp after cke goes high. power - down exit latency is defined in section 8 .7 .1 lpddr2 ac timing table. 7.4.25.1 basic p ower d own e ntry and e xit t iming note: input clock frequency may be changed or the input clock stopped during power - down, provided that upon exiting power - down, the clock is stable and within s pecified limits for a minmum of 2 clock cycles prior to power - down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade . 2 t c k ( m i n ) t i h c k e t c k e ( m i n ) t i s c k e t i h c k e v a l i d e n t e r p d n o p v a l i d e x i t p d i n p u t c l o c k f r e q u e n c y m a y b e c h a n g e d o r t h e i n p u t c l o c k s t o p p e d d u r i n g p o w e r - d o w n e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t x p ( m i n ) t i s c k e c k e [ c m d ] c k _ c c k _ t c s _ n t c k e ( m i n ) v a l i d n o p
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 66 - 7.4.25.2 cke i ntensive e nvironment 7.4.25.3 refresh to refresh t iming with cke i ntensive e nvironment note: the pattern shown above can repeat over a long period of time. with this pattern, lpddr2 sdram gu arantees all ac and dc timing & voltage specifications with temperature and voltage drift. c k e t c k e t c k e t c k e t c k e c k _ c c k _ t c k e t c k e t c k e t c k e t c k e [ c m d ] t x p t x p t r e f i r e f r e f c k _ c c k _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 67 - 7.4.25.4 read to p ower - d own e ntry note: cke may be registered low rl + ru(t dqsck(max) /t ck )+ bl/2 + 1 clock cycles after the clock on which the read command is registered . 7.4.25.5 read with a uto p recharge to p ower - d own e ntry note: cke may be registered low rl + ru(t dqsck(max) /t ck )+ bl/2 + 1 clock cycles after the clock on which the read command is r egistered . t 0 t 1 t 2 t x t x + 1 t x + 2 t x + 9 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t x + 8 t x + 9 t x + 8 t x + 7 t x + 6 t x + 5 t x + 4 t x + 3 t x + 2 t x + 1 t x t 2 t 1 t 0 r l r l t i s c k e t i s c k e r d r d q q q q q q q q q q q q r e a d o p e r a t i o n s t a r t s w i t h a r e a d c o m m a n d a n d c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n . c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n . c k e [ c m d ] c k e [ c m d ] d q d q c k _ c c k _ t d q s _ t d q s _ c d q s _ t d q s _ c t 0 t 1 t 2 t x t x + 1 t x + 2 t x + 9 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t x + 8 q q q q q q q q q q q q r d a r d a p r e p r e t x + 9 t x + 8 t x + 7 t x + 6 t x + 4 t x + 5 t x + 3 t x + 2 t x + 1 t x t 2 t 1 t 0 [ c m d ] c k e d q d q c k e [ c m d ] r l r l c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n . c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n . b l = 4 b l = 8 s t a r t i n t e r n a l p r e c h a r g e s t a r t i n t e r n a l p r e c h a r g e b l / 2 w i t h t r t p = 7 . 5 n s & t r a s m i n s a t i s f i e d b l / 2 w i t h t r t p = 7 . 5 n s & t r a s m i n s a t i s f i e d t i s c k e t i s c k e c k _ c c k _ t d q s _ t d q s _ c d q s _ t d q s _ c
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 68 - 7.4.25.6 write to p ower - d own e ntry note: cke may be registered low wl + 1 + bl/2 + ru(t wr /t ck ) clock cycles after the clock on which the write command is registered. 7.4.25.7 write with a uto p recharge to p ower - d own e ntry note: cke may be registered low wl + 1 + bl/2 + ru(t wr /t ck ) + 1 clock cycles after the write command is regist ered. w r b l = 4 d d d d d d d d d d d d w r w l w l t i s c k e t w r [ c m d ] c k e d q [ c m d ] c k e d q t 0 t 1 t m t m + 1 t m + 2 t m + 3 t x + 6 t x t x + 1 t x + 2 t x + 4 t x + 5 t x + 2 t x + 3 t x + 4 t x + 1 t x t m + 5 t m + 4 t m + 3 t m + 2 t m + 1 t m t 1 t 0 c k _ c c k _ t d q s _ t d q s _ c d q s _ t d q s _ c t x + 3 t i s c k e t w r b l = 8 w r a b l = 4 d d d d d d d d d d d d w r a w l w l t w r [ c m d ] c k e d q [ c m d ] c k e d q t 0 t 1 t m t m + 1 t m + 2 t m + 3 t x t x + 1 t x + 2 t x + 2 t x + 3 t x + 4 t x + 1 t x t m + 5 t m + 4 t m + 3 t m + 2 t m + 1 t m t 1 t 0 t x + 3 t x + 4 t x + 5 t x + 6 p r e p r e s t a r t i n t e r n a l p r e c h a r g e s t a r t i n t e r n a l p r e c h a r g e c k _ c c k _ t c k _ c c k _ t d q s _ t d q s _ c d q s _ t d q s _ c t i s c k e t i s c k e b l = 8 t w r
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 69 - 7.4.25.8 refresh c ommand to p ower - d own e ntry note: cke may go low t ihcke after the clock on which the refresh command is registered. 7.4.25.9 activate c ommand to p ower - d own e ntry note: cke may go low t ihcke after the clock on which the activate command is registered . 7.4.25.10 precharge/precharge - a ll c ommand to p ower - d own e ntry note: cke may go low t ihcke after the clock on which the precharge/precharge - all command is registered . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 r e f t i h c k e t i s c k e c k e [ c m d ] c k _ c c k _ t t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 a c t t i h c k e t i s c k e c k e [ c m d ] c k _ c c k _ t t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 p r e t i h c k e t i s c k e c k e [ c m d ] c k _ c c k _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 70 - 7.4.25.11 mode register read to p ower - d own e ntry note: cke may be registered low rl + ru(t dqsck (max) /t ck )+ bl/2 + 1 clock cycles after the clock on which the mode register read command is registered . 7.4.25.12 mrw c ommand to p ower - d own e ntry note: cke may be registered low t mrw after the clock on which the mode register write command is registered . 7.4.26 deep power - down deep power - down is entered when cke is registered low with cs_n low, ca0 high, ca1 high, and ca2 low at the rising edge of clock. a nop command must be driven in the clock cycle following the power - down command. cke is not allowed to go low while mode register, read, or write operations are in progress. all banks must be in idle state with no activity on th e data bus prior to entering the deep power down mode. during deep power - down, cke must be held low. in deep power - down mode, all input buffers except cke, all output buffers, and the power supply to internal circuitry may be disabled within the sdram. al l power supplies must be within specified limits prior to exiting deep power - down. v refdq and v refca may be at any level within minimum and maximum levels (see 8 .1 absolute maximum dc ratings ). h owever prior to exiting deep power - down, vref must be within specified limits ( s ee 8 .2.1.1 recommended dc operating conditions ). t 0 t 1 t 2 t x t x + 1 t x + 2 t x + 9 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t x + 8 r l t i s c k e m r r q q q q m o d e r e g i s t e r r e a d o p e r a t i o n s t a r t s w i t h a m r r c o m m a n d a n d c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n . c k _ c c k _ t d q s _ t d q s _ c [ c m d ] c k e d q t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 m r w t i s c k e c k e c a n g o t o l o w t m r w a f t e r a m o d e r e g i s t e r w r i t e c o m m a n d c k e [ c m d ] t m r w c k _ c c k _ t
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 71 - the contents of the sdram may be lost upon entry into deep power - down mode. the deep power - down state is exited when cke and cs_n are registered high, while meeting t iscke with a stable clock input. the sdram must be fully re - initialized by controller as described in the power up initialization sequence. the sdram is ready for normal operation after the initialization sequence . 7.4.26.1 deep p ower d own e ntry and e xit t iming note s : 1. initialization sequence may start at any time after t c . 2. t init3 and t c refer to timings in the lpddr2 initialization sequence. for more detail, see section 7 .2 power - up, initialization, and power - off . 3. input clock frequency may be changed or the input clock stopped during deep power - down, provided that upon exiting deep power - down, the clock is stable and wit hin specified limits for a minmum of 2 clock cycles prior to deep power - down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade. 7.4.27 input c lock s top and f requency c hange lpddr2 devices support input clock frequency change during cke low under the following conditions: ? t ck(abs)min is met for each clock cycle; ? refresh requirements apply during clock frequency change; ? during clock frequency change, only refab or refpb commands may be executing; ? any ac tivate, or precharge commands have executed to completion prior to changing the frequency; ? the related timing conditions (t rcd , t rp ) have been met prior to changing the frequency; ? the initial clock frequency shall be maintained for a minimum of 2 clock cycles after cke goes low; ? the clock satisfies t ch(abs) and t cl(abs) for a minimum of 2 clock cycles prior to cke going high. after the input clock frequency is changed and cke is held high, additional mrw commands may be required to set the wr, rl etc . these settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. 2 t c k ( m i n ) t d p d t i s c k e t i h c k e n o p e n t e r d p d n o p r e s e t e x i t d p d i n p u t c l o c k f r e q u e n c y m a y b e c h a n g e d o r t h e i n p u t c l o c k s t o p p e d d u r i n g d e e p p o w e r - d o w n e n t e r d e e p p o w e r - d o w n m o d e e x i t d e e p p o w e r - d o w n m o d e t i s c k e c k e [ c m d ] c s _ n n o p t i n i t 3 = 2 0 0 s ( m i n ) n o p t c c k _ c c k _ t t r p
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 72 - lpddr2 devices support clock stop during cke low under the following conditions: ? ck_t is held low and ck_c is held high during clock stop; ? refr esh requirements apply during clock stop; ? during clock stop, only refab or refpb command s may be executing; ? any activate, or precharge commands have executed to completion prior to stopping the clock; ? the related timing conditions (t rcd , t rp ) have been met prior to stopping the clock; ? the initial clock frequency shall be maintained for a minimum of 2 clock cycles after cke goes low; ? the clock satisfies t ch(abs) and t cl(abs) for a minimum of 2 clock cycles prior to cke going high. lpddr2 devices support input clock frequency change during cke high under the following conditions: ? t ck(abs)min is met for each clock cycle; ? refresh requirements apply during clock frequency change; ? any activate, read, write, precharge, mode register write, or mode register read commands must have executed to completion, including any associated data bursts prior to changing the frequency; ? the related timing conditions (t rcd , t wr , t wra , t rp , t mrw , t mrr , etc.) have been met prior to changing the frequency; ? cs _n shall be held high during clock frequency change; ? during clock frequency change, only refab or refpb commands may be executing; ? the lpddr2 device is ready for normal operation after the clock satisfies t ch(abs) and t cl(abs) for a minimum of 2t ck + t xp . after the input clock frequency is changed, additional mrw commands may be required to set the wr, rl etc. these settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. lpddr2 devices support clock stop duri ng cke high under the following conditions: ? ck_t is held low and ck_c is held high during clock stop; ? cs_n shall be held high during clock clock stop; ? refresh requirements apply during clock stop; ? during clock stop, only refab or refpb commands may be executing; ? any activate, read, write, precharge, mode register write, or mode register read commands must have executed to completion, including any associated data bursts prior to stopping the clock; ? the related timing conditions (t rcd , t wr , t wra , t rp , t mrw , t mrr , etc.) have been met prior to stopping the clock; ? the lpddr2 device is ready for normal operation after the clock is restarted and satisfies t ch(abs) and t cl(abs) for a minimum of 2 t ck + t xp . 7.4.28 no operation c ommand the purpose of the no operation command (nop) is to prevent the lpddr2 device from registering any unwanted command between operations. only when the cke level is constant for clock cycle n - 1 and clock cycle n, a nop command may be issued at clock cycle n. a nop command has two possible encodings: 1. cs_n high at the clock rising edge n. 2. cs_n low and ca0, ca1, ca2 high at the clock rising edge n. the no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.5 truth tables the truth tables provide complementary information to the state diagram , they clarify the device behavior and the applied restrictions when considering the actual state of all the banks . operation or timing that is not specified is illegal, a nd after such an event, in order to guarantee proper operation, the lpddr2 device must be powered down and then restarted through the specified initialization sequence before normal operation can continue .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 73 - 7.5.1 command truth table command command pin s ddr ca p in s (10) ck _t edge cke cs_n ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 ca9 ck_t(n - 1) ck_t(n) mrw h h l l l l l ma0 ma1 ma2 ma3 ma4 ma5 x ma6 ma7 op0 op1 op2 op3 op4 op5 op6 op7 mrr h h l l l l h ma0 ma1 ma2 ma3 ma4 ma5 x ma6 ma7 x refresh ( per bank) 11 h h l l l h l x x x refresh (all bank) h h l l l h h x x x enter self refresh h l l l l h x x x x activate (bank) h h l l h r8 r9 r10 r11 r12 ba0 ba1 ba2 x r0 r1 r2 r3 r4 r5 r6 r7 r13 r14 write (bank) h h l h l l rfu rfu c1 c2 ba0 ba1 ba2 x ap * 3,4 c3 c4 c5 c6 c7 c8 c9 c10 c11 read (bank) h h l h l h rfu rfu c1 c2 ba0 ba1 ba2 x ap * 3,4 c3 c4 c5 c6 c7 c8 c8 c10 c11 precharge ( per bank , all bank ) h h l h h l h ab x x ba0 ba1 ba2 x x bst h h l h h l l x x x enter deep power down h l l h h l x x x x nop h h l h h h x x x maintain pd,sref,dpd (nop) l l l h h h x x x nop h h h x x x maintain pd,sref,dpd (nop) l l h x x x enter power down h l h x x x x exit pd, sref,dpd l h h x x x x
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 74 - note s : 1. all lpddr2 commands are defined by states of cs_n, ca0, ca1, ca2, ca3, and cke at the rising edge of the clock . 2. for lpddr2 sdram, bank addresses ba0, ba1, ba2 (ba) determine which bank is to be operated upon . 3. ap is significant only to sdram. 4. ap high during a read or write command indicates that an auto - precharge w ill occur to the bank associated with the read or write command. 5. x means h or l (but a defined logic level) . 6. self refresh exit and deep power down exit are asynchronous. 7. v ref must be between 0 and v ddq during self refresh and deep power down operation. 8. caxr refers to command/address bit x on the rising edge of clock. 9. caxf refers to command/address bit x on the falling edge of clock. 10. cs_n and cke are sampled at the rising edge of clock. 11. per bank refresh is only allowed in devices with 8 banks. 12. the le ast - significant column address c0 is not transmitted on the ca bus, and is implied to be zero. 13. ab highduring precharge command indicates that all bank precharge will occur. in this case, bank address is do - not - care. 7.5.2 cke truth table note s : 1. cken is the logic state of cke at clock rising edge n; cken - 1 was the state of cke at the previous clock edge . 2. cs_n is the logic state of cs_n at the clock rising edge n; 3. current state is the state of the lpddr2 device immediately prior to clock edge n. 4. command n is the command registered at clock edge n, and operation n is a result of command n. 5. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document . 6. power down exit time (t xp ) should elapse before a command other than nop is issued. 7. self - refresh exit time (t xsr ) should elapse before a command other than nop is issued. 8. the deep power - down exit procedure must be followed as discussed in the dee p power - down section of the func tional description. 9. the clock must toggle at least once during the t xp period. 10. the clock must toggle at least once during the t xsr time. 11. x means dont care. 12. upon exiting resetting power down, the device will return to th e idle state if t init5 has expired. device current state *3 cken - 1 *1 cken *1 cs_n *2 command n *4 operation n *4 device next state note s active power down l l x x maintain active power down active power down l h h nop exit active power down active 6, 9 idle power down l l x x maintain idle power down idle power down l h h nop exit idle power down idle 6, 9 resetting power down l l x x maintain resetting power down resetting power down l h h nop exit resetting power down idle or resetting 6, 9, 12 deep power down l l x x maintain deep power down deep power down l h h nop exit deep power down power on 8 self refresh l l x x maintain self refresh self refresh l h h nop exit self refresh idle 7, 10 bank(s) active h l h nop enter active power down active power down all banks idle h l h nop enter idle power down idle power dow h l l enter self refresh enter self refresh self refresh h l l deep power down enter deep power down deep power down resetting h l h nop enter resetting power down resetting power down others states h h refer to the command truth table
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 75 - 7.5.3 current state bank n - command to bank n truth table current state command operation next state note s any nop continue previous operation current state idle activate select and activate row active refresh ( per bank) begin to refresh refreshing( per bank) 6 refresh (all bank) begin to refresh refreshing(all bank) 7 mrw load value to mode register mr writing 7 mrr read value from mode register idle mr reading reset begin device auto - initialization resetting 7 , 8 precharge deactivate row in bank or banks precharging 9 , 1 5 row active read select column, and start read burst reading write select column, and start write burst writing mrr read value from mode register active mr reading precharge deactivate row in bank or banks precharging 9 reading read select column, and start new read burst reading 10 , 11 write select column, and start write burst writing 10 , 1 1 , 1 2 bst read burst terminate active 1 3 writing write select column, and start new write burst writing 10 , 1 1 read select column, and start read burst reading 10 , 1 1 , 1 4 bst write burst terminate active 1 3 power on reset begin device auto - initialization resetting 7 , 9 resetting mrr read value from mode register resetting mr reading note s : 1. the table applies when both cken - 1 and cken are high, and after t xsr or t xp has been met if the previous state was power down . 2. all states and sequences not shown are illegal or reserved . 3. current state definitions: idle: the bank or banks have been precharged, and t rp has been met. active: a row in the bank has been activated, and t rcd has been met. no data bursts / accesses and no register accessesare in progress. reading: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. writing: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same b ank. nop commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other banks are determined by its current state and 7 . 5 .3 current state bank n - command to bank n truth table , and according to 7 . 5 . 4 current state bank n - command to bank m truth table . precharging: starts with the registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state . row activating: starts with registration of a n activate command and ends when t rcd is met. once t rcd is met, the bank will be in the active state . read with ap enabled: starts with the registration of the read command with auto precharge enabled and ends when t rp has been met. once t rp has been met , the bank will be in the idle state . write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 76 - 5. the following states must not be interrupted by any executable command; nop commands must be applied to each positive clock edge during these states. refreshing ( per bank): starts with regist ration of a refresh ( per bank) command and ends when t rfc p b is met. once t rfc p b is met, the bank w ill be in an idle state . refreshing (all bank): starts with regist ration of a refresh (all bank) command and ends when t rfcab is met. once t rfcab is met, the device will be in an all banks idle state . idle mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the idle state . resetting mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the re setting state . active mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the active state. mr writing: starts with the registration of a mrw command and ends when t mrw has been met. once t mrw has been met, the bank will be in the idle state. precharging all: starts with the registration of a precharge - all command and ends when t rp is met. once t rp is met, the bank will be in the idle state. 6. bank - specific; requires that the bank is idle and no bursts are in progress. 7. not bank - specific; requires that all banks are idle and no bursts are in progress . 8. not bank - specific reset command is achieved through mode register write command . 9. this command may or may not be bank specific . if all banks are being precharged, they must be in a valid state for pre - charging . 10. a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled . 11. the new read or write command could be auto pre charge enabled or auto precharge disabled . 12. a write command may be applied after the completion of the read burst; otherwise, a bst must be used to end the read prior to asserting a write command . 13. not bank - specific. burst terminate (bst) command affects the most recent read/write burst started by the most recent read/write command, regardless of bank. 14. a read command may be applied after the completion of the write burst; otherwise, a bst must be used to end the write prior to asserting a read command . 15. if a precharge command is issued to a bank in the idle state, t rp shall still apply .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 77 - 7.5.4 current state bank n - command to bank m truth table current state of bank n command for bank m operation next state for bank m note s any nop continue previous operation current state of bank m idle any any command allowed to bank m - 18 row activating, active, or precharging activate select and activate row in bank m active 7 read select column, and start read burst from bank m reading 8 write select column, and start write burst to bank m writing 8 precharge deactivate row in bank or banks precharging 9 mrr read value from mode register idle mr reading or active mr readin 10, 11, 13 bst read or write burst terminate an ongoing read/write from/to bank m active 18 reading (autoprecharge disabled) read select column, and start read burst from bank m reading 8 write select column, and start write burst to bank m writing 8, 14 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 writing (autoprecharge disabled) read select column, and start read burst from bank m reading 8, 16 write select column, and start write burst to bank m writing 8 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 reading with autoprecharge read select column, and start read burst from bank m reading 8, 15 write select column, and start write burst to bank m writing 8, 14, 15 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 writing with autoprecharge read select column, and start read burst from bank m reading 8, 15, 16 write select column, and start write burst to bank m writing 8, 15 activate select and activate row in bank m active precharge deactivate row in bank or banks precharging 9 power on reset begin device auto - initialization resetting 12, 17 resetting mrr read value from mode register resetting mr reading note s : 1. the table applies when both cken - 1 and cken are high, and after t xsr or t xp has been met if the previous state was self refresh or power down . 2. all states and sequences not shown are illegal or reserved . 3. current state definitions: idle: the bank has been precharged, and t rp has been met . active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress . reading: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated . writing: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 78 - 4. refresh, self - refresh, and mode register write commands may only be issued when all bank are idle . 5. a burst terminate (bst) command cannot be issued to another bank; it applies to the bank represented by the current state only . 6. the following states must not be interrupted by any executable command; nop commands must be applied during each clock cycle while in these states: idle mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the idle state . resetting mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the resetting state . active mr reading: starts with the registration of a mrr command and ends when t mrr has been met. once t mrr has been met, the bank will be in the active state . mr writing: starts with the registration of a mrw command and ends when t mrw has been met. once t mrw has been met, the bank will be in the idle state . 7. t rrd must be met between activate command to bank n and a subsequent activate command to bank m . 8. reads or writes lis ted in the command column include reads and writes with auto precharge enabled and reads and writes with auto precharge disabled . 9. this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for pre - charging . 10. mrr is allowed during the row activating state (row activating starts with registration of an activate command and ends when t rcd is met) . 11. mrr is allowed during the precharging state. (precharging starts with registration of a precharge command a nd ends when t rp is met . 12. not bank - specific; requires that all banks are idle and no bursts are in progress. 13. the next state for bank m depends on the current state of bank m (idle, row activating, precharging, or active). the reader s hall note that the stat e may be in transition when a mrr is issued. therefore, if bank m is in the row activating state and precharging, the next st ate may be active and precharge dependent upon t rcd and t rp respectively . 14. a write command may be applied after the completion of th e read burst ; otherwise a bst must be issued to end the read prior to asserting a write command . 15. read with auto precharge enabled or a write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restrictio ns in 7 .4.14.2 precharge & auto precharge c larification table are followed . 16. a read command may be applied after the completion of the write burst; otherwise, a bst must be issued to end the write prior to asserting a read command . 17. reset command is achieved through mode register write command . 18. bst is allowed only if a read or write burst is ongoing . 7.5.5 data m ask truth table name (functional) dm dqs note write enable l valid 1 write inhibit h x 1 note: 1. used to mask write data, provided coincident with the corresponding data .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 79 - 8. electrical character istic 8.1 absolute maximum dc ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol min max units notes v dd1 supply voltage relative to v ss v dd1 - 0.4 + 2.3 v 2 v dd2 supply voltage relative to v ss v dd2 - 0.4 + 1.6 v 2 v ddca supply voltage relative to v ssca v ddca - 0.4 + 1.6 v 2, 4 v ddq supply voltage relative to v ssq v ddq - 0.4 + 1.6 v 2, 3 voltage on any ball relative to v ss v in , v out - 0.4 + 1.6 v storage temperature t stg - 55 + 125 c 5 note s : 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . 2. see power ramp in section 7 .2.1 power ramp and device initialization for relationships between power supplies . 3. v refdq 0.6 x v ddq ; however, v refdq may be v ddq provided that v refdq 300mv. 4. v refca 0.6 x v ddca ; however, v refca may be v ddca provided that v refca 300mv. 5. storage temperature is the case surface temperature on the center/top side of the lpddr2 device. for the measurement conditio ns, please refer to jesd51 - 2 standard . 8.2 ac & dc o perating c onditions operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the lpddr2 device must be powered down and then restarted through the specialized ini tialization sequence before normal operation can continue. 8.2.1 recommended dc operating conditions 8.2.1.1 recommended dc operating conditions symbol lpddr2 - s 4 b dram unit min typ max v dd1 1.70 1.80 1.95 core power1 v v dd2 1.14 1.20 1. 30 core power2 v v ddca 1.14 1.20 1. 30 input buffer power v v ddq 1.14 1.20 1. 30 i/o buffer power v note: v dd1 uses significantly less power than v dd2 .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 80 - 8.2.2 input leakage current parameter/condition symbol min max unit note s input leakage current for ca, cke, cs_n, ck_t, ck_c any input 0v v in v ddca (all other pin s not under test = 0v) i l - 2 2 a 2 v ref supply leakage current v refdq = v ddq /2 or v refca = v ddca /2 (all other pin s not under test = 0v) i vref - 1 1 a 1 note s : 1. the minimum limit requirement is for testing purposes. the leakage current on v refca and v refdq pin s should be minimal . 2. although dm is for input only, the dm leakage shall match the dq and dqs_t/dqs_c output leakage specification . 8.2.3 operating temperature conditions parameter/condition symbol min max unit standard t oper - 40 85 c extended 85 1 0 5 c note s : 1. operating temperature is the case surface temperature on the center/top side of the lpddr2 device. for the measurement conditions, please refer to jesd51 - 2 standard. 2. some applications require operation of lpddr2 in the maximum temperature conditons in the extended temperature range between 85 c and 1 0 5 c case temperature. for lpddr2 devices, some derating is neccessary to operate in this range. s ee the mr4 device te mperature (ma[7:0] = 04h) table . 3. either the device operating temperature or the temperature sensor (see section 7.4.21 temperature sensor ) may be used to set an appropriate refresh rate, determine the need for ac timing derating and/or monitor the operating temperature. when using the temperature sensor, the actual device case temperature may be higher than the t oper rating that applies for the standard or extended temperature ranges. for example, t case may be above 85oc when the temperature sensor indicates a temperature of less than 85 c . 4. all parts list in section 3 ordering information table will not guarantee to meet ac specification in the range of extended temperature range. 8.2.4 ac and dc input measurement levels 8.2.4.1 ac and dc logic input levels for single - ended signals 8.2.4.1.1 single - ended ac and dc input levels for ca and cs_n inputs symbol parameter lpddr2 - 800/1066 unit note s min max v ih ca (ac) ac input logic high v ref + 0.220 note 2 v 1 , 2 v il ca (ac) ac input logic low note 2 v ref - 0.220 v 1 , 2 v ih ca (dc) dc input logic high v ref + 0.130 v dd ca v 1 v il ca (dc) dc input logic low v ss ca v ref - 0.130 v 1 v ref ca (dc) reference voltage for ca and cs_n inputs 0.49 * v dd ca 0.51 * v dd ca v 3, 4 note s : 1. for ca and cs_n input only pin s. v ref = v refca (dc) . 2. see section 8 .2.5.5 overshoot and undershoot specifications . 3. the ac peak noise on v refca may not allow v refca to deviate from v refca (dc) by more than 1% v ddca (for reference: approx. 12 mv) . 4. for reference: approx. v ddca /2 12 mv .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 81 - 8.2.4.1.2 single - ended ac and dc input levels for cke symbol parameter min max unit note v ihcke cke input high level 0.8 * v ddca note 1 v 1 v ilcke cke input low level note 1 0.2 * v ddca v 1 note 1 : see section 8 .2.5.5 overshoot and undershoot specifications . 8.2.4.1.3 single - ended ac and dc input levels for dq and dm symbol parameter lpddr2 - 1066 / lpddr2 - 800 unit note s min max v ihdq (ac) ac input logic high v ref + 0.220 note 2 v 1 , 2 v ildq (ac) ac input logic low note 2 v ref - 0.220 v 1 , 2 v ihdq (dc) dc input logic high v ref + 0.130 vddq v 1 v ildq (dc) dc input logic low vss q v ref - 0.130 v 1 v refdq (dc) reference voltage for dq, dm inputs 0.49 * v ddq 0.51 * v ddq v 3, 4 note s : 1. for dq input only pin s. vref = v refdq (dc) . 2. see section 8 .2.5.5 overshoot and undershoot specifications . 3. the ac peak noise on v refdq may not allow vrefdq to deviate from v refdq (dc) by more than 1% v ddq (for reference: approx. 12 mv). 4. for reference: approx. v ddq /2 12 mv . 8.2.4.2 vref tolerances the dc tolerance limits and ac - noise limits for the reference voltages v refca and v refdq are illustrated in below v ref (dc) t olerance and v ref ac - n oise l imits f igure . it shows a valid reference voltage v ref(t) as a function of time. (v ref stands for v refca and v refdq likewise). v dd stands for v ddca for v refca and v ddq for v refdq . v ref(dc) is the linear average of v ref(t) over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of v ddq or v ddca also over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in 8 .2.4.1.1 single - ended ac and dc input levels for ca and cs_n inputs table . furthermore v ref(t) may temporarily deviate from v ref(dc) by no more than 1% v dd . v ref(t) cannot track noise on v ddq or v ddca if this would send v ref outside these specifications.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 82 - 8.2.4.2.1 v ref(dc) t olerance and v ref ac - n oise l imits the voltage levels for setup and hold time measurements v ih(ac) , v ih(dc) , v il(ac) and v il(dc) are dependent on v ref . v ref shall be understood as v ref(dc) , as defined in above v ref (dc) t olerance and v ref ac - n oise l imits f igure . this clarifies that dc - variations of v ref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is me asured. devices will function correctly with appropriate timing deratings with v r ef outside these specified levels so long as v r ef is maintained between 0.44 x v ddq (or v ddca ) and 0.56 x v ddq (or v ddca ) and so long as the controller achieves the required single - ended ac and dc input levels from instantaneous vref ( see 8 .2.4.1.1 single - ended ac and dc input levels for ca and cs_n inputs table and 8 .2. 4.1.3 single - ended ac and dc input levels for dq and dm table ) therefore, system timing and voltage budgets need to account for v r ef de viations outs ide of this range. this also clarifies that the lpddr2 setup/hold specification and derating values need to include time and voltage associated with v ref ac - noise. timing and voltage effects due to ac - noise on v ref up to the specified limit ( 1% of v dd ) are included in lpddr2 timings and their associated deratings. v r e f a c - n o i s e v r e f ( d c ) m a x v r e f ( d c ) m i n v r e f ( t ) v d d v s s v r e f ( d c ) v o l t a g e t i m e v d d / 2
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 83 - 8.2.4.3 input signal 8.2.4.3.1 lpddr2 - 800/1066 input signal note s : 1. numbers reflect nominal values. 2. for ca0 - 9, ck_t, ck_c, and cs_n, v dd stands for v ddca . for dq, dm, dqs_t, and dqs_c, v dd stands for v ddq . 3. for ca0 - 9, ck_t, ck_c, and cs_n, v ss stands for v ssca . for dq, dm, dqs_t, and dqs_c, v ss stands for v ssq . v i l a n d v i h l e v e l s w i t h r i n g b a c k 1 . 5 5 0 v 1 . 2 0 0 v 0 . 8 2 0 v 0 . 7 3 0 v 0 . 6 2 4 v 0 . 6 1 2 v 0 . 6 0 0 v 0 . 5 8 8 v 0 . 5 7 6 v 0 . 4 7 0 v 0 . 3 8 0 v 0 . 0 0 0 v - 0 . 3 5 0 v v s s C 0 . 3 5 v v s s v i l ( a c ) v i l ( d c ) v r e f C a c n o i s e v r e f C d c e r r o r v r e f + d c e r r o r v r e f + a c n o i s e v i h ( d c ) v i h ( a c ) v d d v d d + 0 . 3 5 v m i n i m u m v i l a n d v i h l e v e l s v i h ( a c ) 0 . 8 2 0 v 0 . 7 3 0 v v i h ( d c ) 0 . 6 2 4 v 0 . 6 1 2 v 0 . 6 0 0 v 0 . 5 8 8 v 0 . 5 7 6 v 0 . 4 7 0 v 0 . 3 8 0 v v i l ( d c ) v i l ( a c )
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 84 - 8.2.4.4 ac and dc logic input levels for differential signals 8.2.4.4.1 differential s ignal d efi nition figure of definition of d ifferential ac - s wing and t ime above ac - l evel t dvac 8.2.4.4.2 differential swing requirements for clock (ck_t - ck_c) and strobe (dqs_t - dqs_c) table of differential ac and dc input levels symbol parameter lpddr2 - 800/1066 unit note s min max v ihdiff (dc) differential input high 2 x (v ih (dc) - v ref ) n ote 3 v 1 v ildiff (dc) differential input logic low note 3 2 x (v il (dc) - v ref ) v 1 v ihdiff (ac) differential input high ac 2 x (v ih (ac) - v ref ) note 3 v 2 v ildiff (ac) differential input low ac n ote 3 2 x (v il ( a c) - v ref ) v 2 note s : 1. used to define a differential signal slew - rate . for ck_t - ck_c use v ih /v il ( d c) of ca and v refca ; for dqs_t - dqs_c, use v ih /v il ( d c) of dqs and v refdq ; if a reduced d c - high or d c - low level is used for a signal group, then the reduced level applies also here . 2. for ck_t - ck_c use v ih /v il (ac) of ca and v refca ; for dqs_t - dqs_c, use v ih /v il (ac) of dqs and v refdq ; if a reduced ac - high or ac - low level is used for a signal g roup, then the reduced level applies also here . 3. these values are not defined, however the single - ended signals ck_t, ck_c, dqs_t, and dqs_c need to be within the respective limits (v ih (dc) max, v il (dc)min) for single - ended signals as well as the limitation s for overshoot and undershoot. refer to section 8 .2.5.5 overshoot and undershoot specifications . 4. for ck_t and ck_c, vref = v refca(dc) . for dqs_t and dqs_c, vref = v refdq(dc) . v i h d i f f ( a c ) m i n h a l f c y c l e d i f f e r n t i a l v o l t a g e v i l d i f f ( d c ) m a x v i l d i f f ( a c ) m a x v i h d i f f ( d c ) m i n t d v a c t i m e c k _ t - c k _ c d q s _ t - d q s _ c t d v a c 0 . 0
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 85 - table of allowed t ime b efore r ingback (t dvac ) for ck_t - ck_c and dqs_t - dqs_c slew rate [v/ ns ] t dvac [ ps ] @ |v ih diff(ac) or v i l diff(ac)| = 440mv > 4.0 175 4.0 170 3.0 167 2.0 163 1.8 162 1.6 161 1.4 159 1.2 155 1.0 150 < 1.0 150 8.2.4.5 single - e nded r equirements for d ifferential s ignals each individual component of a differential signal (ck_t, dqs_t, ck_c, or dqs_c) has also to comply with certain requirements for single - ended signals . ck_t and ck_c shall meet v seh (ac)min / v sel (ac)max in every half - cycle. dqs_t, dqs_c shall meet v seh (ac)min / v sel (ac)max in every half - cycle preceeding and following a valid transition. note that the applicable ac - levels for ca and dqs are different per speed - bin . figure of single - e nded r equirement for d ifferential s ignals v s e l ( a c ) t i m e c k _ t , c k _ d q s _ t , o r d q s _ c v s e h ( a c ) v d d c a o r v d d q v s e h ( a c ) m i n v d d c a / 2 o r v d d q / 2 v s s c a o r v s s q v s e l ( a c ) m a x
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 86 - note that while ca and dq signal requirements are with respect to vref, the single - ended components of differential signals have a requirement with respect to v ddq /2 for dqs_t , dqs_ c and v ddca /2 for ck_t , ck_c; this is nominally the same. the transition of single - ended signals through the ac - levels is used to measure setup time. for single - ended components of differential signals the requirement to reach v sel (ac)max, v seh (ac)min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. the signal ended requirements for ck_t , ck_c , dqs_t and dqs_c are found in 8 .2.4.1.1 single - ended ac and dc input levels for ca and cs_n inputs table and 8 .2.4.1.3 single - ended ac and dc input levels for dq and dm table , respectively . table of single - e nded l evels for ck_t, dqs_t, ck_c, dqs_c symbol parameter lpddr2 - 800/1066 unit note s min max v seh(ac) single - ended high - level for strobes (v ddq / 2) + 0.220 n ote 3 v 1, 2 single - ended high - level for ck_t, ck_c (v ddca / 2) + 0.220 n ote 3 v 1, 2 v sel(ac) single - ended low - level for strobes n ote 3 (v ddq / 2) - 0.220 v 1, 2 single - ended low - level for ck_t, ck_c n ote 3 (v ddca / 2) - 0.220 v 1, 2 note s : 1. for ck_t, ck_c use v seh /v sel (ac) of ca; for strobes (dqs0_t, dqs0_c, dqs1_t, dqs1_c, dqs2_t, dqs2_c, dqs3_t, dqs3_c) use v ih /v il (ac) of dqs . 2. v ih (ac)/v il (ac) for dqs is based on v refdq ; v seh (ac)/v sel (ac) for ca is based on v refca ; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined, however the single - ended signals ck_t, ck_c, dqs0_t, dqs0_c, dqs1_t, dqs1_c, d qs2_t, dqs2_c, dqs3_t, dqs3_c need to be within the respective limits (v ih (dc) max, v il (dc)min) for single - ended signals as well as the limitations for overshoot and undershoot. refer to section 8 .2.5.5 overshoot and undershoot specifications . 8.2.4.6 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck_t, ck_c and dqs_t, dqs_c) must meet the requirements of above single - ended levels for ck_t, dqs_t, ck_c, dqs_c table . the differential input cross point voltage v ix is measured from the actual cross point of true and complement signals to the midlevel between of v dd and v ss . figure of vix definition v d d c a / 2 o r v d d q / 2 v s s c a o r v s s q v d d c a o r v d d q c k _ c , d q s _ c c k _ t , d q s _ t v i x v i x v i x
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 87 - table of cross p oint v oltage for d ifferential i nput s ignals (ck, dqs) symbol parameter lpddr2 - 800/1066 unit note s min max v ixca differential input cross point voltage relative to v ddca /2 for ck_t, ck_c - 120 120 mv 1, 2 v ixdq differential input cross point voltage relative to v ddq /2 for dqs_t, dqs_c - 120 120 mv 1, 2 note s : 1. the typical value of v ix(ac) is expected to be about 0.5 v dd of the transmitting device, and v ix(ac) is expected to track variations in v dd . v ix(ac) indicates the voltage at which differential input signals must cross . 2. for ck_t and ck_c, v ref = v refca(dc) . for dqs_t and dqs_c, v ref = v refdq(dc) . 8.2.4.7 slew rate definitions for single - ended input signals see section 8 .7 .2 ca and cs_n s etup, hold and derating for single - ended slew rate definitions for address and command signals. see section 8 .7 .3 data setup, hold and slew rate derating for single - ended slew rate definitions for data signals. 8.2.4.8 slew rate definitions for differential input signals input slew rate for differential signals (ck_t, ck_c and dqs_t, dqs_c) are defined and measured a s shown in below t able and f igure. table of differential input slew rate definition description measured defined by from to differential input slew rate for rising edge (ck_t - ck_c and dqs_t - dqs_c). v ildiffmax v ihdiffmin [v ihdiffmin - v ildiffmax ] / deltatrdiff differential input slew rate for falling edge (ck_t - ck_c and dqs_t - dqs_c). v ihdiffmin v ildiffmax [v ihdiffmin - v ildiffmax ] / deltatfdiff note: the differential signal (i.e. ck_t - ck_c and dqs_t - dqs_c) must be linear between these thresholds . figure of differential input slew rate definition for dqs_t, dqs_c and ck_t, ck_c d e l t a t f d i f f d e l t a t r d i f f 0 v i l d i f f m a x v i h d i f f m i n d i f f e r e n t i a l i n p u t v o l t a g e ( i . e . d q s _ t - d q s _ c ; c k _ t - c k _ c )
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 88 - 8.2.5 ac and dc output measurement levels 8.2.5.1 single ended ac and dc output levels table of single - e nded ac and dc output levels symbol parameter lpddr2 - 800/1066 unit note s v oh(dc) dc output high measurement level (for iv curve linearity) 0.9 x v ddq v 1 v ol(dc) dc output low measurement level (for iv curve linearity) 0.1 x v ddq v 2 v oh(ac ) ac output high measurement level (for output slew rate) v ref dq + 0.12 v v ol(ac) ac output low measurement level (for output slew rate) v ref dq - 0.12 v i oz output leakage current (dq, dm, dqs_t, dqs_c) (dq, dqs_t, dqs_c are disabled;0 v v out v ddq ) m in - 5 a max +5 mm pupd delta ron between pull - up and pull - down for dq/dm miin - 15 % max +15 note s : 1. i oh = - 0.1ma . 2. i ol = + 0.1ma . 8.2.5.2 differential ac and dc output levels table of differential ac and dc output levels of (dqs_t, dqs_c) symbol parameter lpddr2 - 800/1066 unit note s v ohdiff(ac) ac differential output high measurement level (for output sr) + 0.2 0 x v ddq v v oldiff(ac) ac differential output low measurement level (for output sr) - 0.2 0 x v ddq v note s : 1. i oh = - 0.1ma. 2. i ol = + 0.1ma . 8.2.5.3 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol(ac) and v oh(ac) for single ended signals as shown in below t able and f igure . table of single - e nded output slew rate definition description measured defined by from to single - ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) - v ol(ac )] / deltatrse single - ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) - v ol(ac) ] / deltatfse note: output slew rate is verified by design and characterization, and may not be subject to production test.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 89 - figure of single ended output slew rate definiton table of output slew rate ( s ingle - e nded) symbol parameter lpddr2 - 800/1066 unit s min max s rqse single - ended output slew rate (r on = 40 30%) 1.5 3.5 v/ ns s rqse single - ended output slew rate (r on = 60 30%) 1.0 2.5 v/ ns output slew - rate matching ratio (pull - up to pull - down) 0.7 1.4 description: sr: slew rate q: query output (like in dq, which stands for data - in, query - output) se: single - ended signals note s : 1. measured with output reference load. 2. the ratio of pull - up to pull - down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. for a given output, it represents the maximum difference between pull - up and pulldown drivers due to process variation. 3. the output slew rate for falling and rising edges i s defined and measured between v ol(ac ) and v oh(ac) . 4. slew rates are measured under normal sso conditions, with 1/2 of dq signals per data byte driving logic high and 1/2 of dq signals per data byte driving logic low. d e l t a t f s e d e l t a t r s e v r e f v o l ( a c ) s i n g l e e n d e d o u t p u t v o l l a g e ( i . e . d q ) v o h ( a c )
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 90 - 8.2.5.4 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v oldiff(ac) and v ohdiff(ac) for differential signals as shown in below t able and f igure . table of differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v oldiff(ac) v ohdiff(ac) [v ohdiff(ac) - v oldiff(ac) ] / deltatrdiff differential output slew rate for falling edge v ohdiff(ac) v oldiff(ac) [v ohdiff(ac) - v oldiff(ac) ] / deltatfdiff note: output slew rate is verified by design and characterization, and may not be subject to production test. figure of differential output slew rate definition table of differential output slew rate symbol parameter lpddr2 - 800/1066 unit s min max s rq diff differential output slew rate (r on = 40 30%) 3.0 7.0 v/ ns s rq diff differential output slew rate (r on = 60 30%) 2.0 5.0 v/ ns description: sr: slew rate q: query output (like in dq, which stands for data - in, query - output) diff : differential signals note s : 1. measured with output reference load. 2. the output slew rate for falling and rising edges is defined and measured between v ol diff (ac) and v oh diff (ac) . 3. slew rates are measured under normal sso conditions, with 1/2 of dq signals per data byte driving logic - high and 1/2 of dq signals per data byte driving logic - low . d e l t a t f d i f f d e l t a t r d i f f 0 v o l d i f f ( a c ) d i f f e r e n t i a l o u t p u t v o l t a g e ( i . e . d q s _ t C d q s _ c ) v o h d i f f ( a c )
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 91 - 8.2.5.5 overshoot and undershoot specifications table of ac overshoot/undershoot specification paramete r lpddr2 unit 1066 933 800 667 533 400 333 maximum peak amplitude allowed for overshoot area. (see f igure below ) max 0.35 v maximum peak amplitude allowed for undershoot area. (see f igure below ) max 0.35 v maximum area above v dd . (see f igure below ) max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 v - ns maximum area below v ss . (see f igure below ) max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 v - ns ( ca0 - 9 , cs_n, cke, ck_t, ck_c, dq, dqs_t, dqs_c, dm ) note s : 1. for ca0 - 9, ck_t, ck_c, cs_n, and cke, v dd stands for v ddca . for dq, dm, dqs_t, and dqs_c, v dd stands for v ddq . 2. for ca0 - 9, ck_t, ck_c, cs_n, and cke, v ss stands for v ssca . for dq, dm, dqs_t, and dqs_c, v ss stands for v ssq . 3. maximum peak amplitude values are referenced from actual v dd and v ss values. 4. maximum area values are referenced from maximum operating v dd and v ss values. f igure of overshoot and undershoot definition note s : 1. for ca0 - 9 , ck_t, ck_c, cs_n, and cke, v dd stands for v ddca . for dq, dm, dqs_t, and dqs_c, v dd stands for v ddq . 2. for ca0 - 9 , ck_t, ck_c, cs_n, and cke, v ss stands for v ssca . for dq, dm, dqs_t, and dqs_c, v ss stands for v ssq . 3. maximum peak amplitude values are referenced from actual v dd and v ss values. 4. maximum area values are referenced from maximum operating v dd and v ss values. v d d v s s o v e r s h o o t a r e a u n d e r s h o o t a r e a m a x i m u m a m p l i t u d e m a x i m u m a m p l i t u d e t i m e ( n s ) v o l t s ( v )
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 92 - 8.2.6 output buffer c haracteristics 8.2.6.1 hsul_12 driver output timing reference load these timing reference loads are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a p roduction tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines termi nated at the tester electronics. figure of hsul_12 driver output reference load for timing and slew rate note: all output timing parameter values (like t dqsck , t dqsq , t qhs , t hz , t rpre etc . ) are reported with respect to this reference load. this reference load is also used to report slew rate. 8.2.6.2 ron pu and ron pd resistor definition ronp u = note: this is under the condition that ron pd is turned off ronp d = note: this is under the condition that ron pu is turned off figure of output driver definition of voltages and currents 0 . 5 x v d d q c l o a d = 5 p f v r e f o u t p u t l p d d r 2 s d r a m v t t = 0 . 5 x v d d q r t t = 5 0 ) ( ) ( C iout abs vout vddq ) ( iout abs vout c h i p i n d r i v e m o d e v d d q v s s q d q o u t p u t d r i v e r i p u i p d r o n p u r o n p d i o u t v o u t t o o t h e r c i r c u i t y r t l i k e r c v , . . .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 93 - 8.2.6.3 ron pu and ron pd characteristics with zq calibration output driver impedance ron is defined by the value of the external reference resistor r zq . nominal r zq is 240 . table of output driver dc electrical characteristics with zq calibration ro n nom resis t o r v o u t min n om max unit n ot e 34.3 ron34pd 0.5 x vddq 0. 8 5 1.00 1.15 rzq/7 1, 2, 3, 4 ron34pu 0.5 x vddq 0. 8 5 1.00 1.15 rzq/7 1, 2, 3, 4 40.0 ron40pd 0.5 x vddq 0. 8 5 1.00 1.15 rzq/6 1, 2, 3, 4 ron40pu 0.5 x vddq 0. 8 5 1.00 1.15 rzq/6 1, 2, 3, 4 48.0 ron48pd 0.5 x vddq 0. 8 5 1.00 1.15 rzq/5 1, 2, 3, 4 ron48pu 0.5 x vddq 0. 8 5 1.00 1.15 rzq/5 1, 2, 3, 4 60.0 ron60pd 0.5 x vddq 0. 8 5 1.00 1.15 rzq/4 1, 2, 3, 4 ron60pu 0.5 x vddq 0. 8 5 1.00 1.15 rzq/4 1, 2, 3, 4 80.0 ron80pd 0.5 x vddq 0. 8 5 1.00 1.15 rzq/3 1, 2, 3, 4 ron80pu 0.5 x vddq 0. 8 5 1.00 1.15 rzq/3 1, 2, 3, 4 12 0.0 ron 12 0pd 0.5 x vddq 0. 8 5 1.00 1.15 rzq/ 2 1, 2, 3, 4 ron 12 0pu 0.5 x vddq 0. 8 5 1.00 1.15 rzq/ 2 1, 2, 3, 4 mismatch between pull - up and pull - down mm pupd - 15.00 +15.00 % 1, 2, 3, 4 , 5 note s : 1. across entire operating temperature range, after calibration. 2. rzq = 240. 3. the tolerance limits are specified after calibration with fixed voltage and temperature. for behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity . 4. pull - do wn and pull - up output driver impedances are recommended to be calibrated at 0.5 x v ddq . 5. mesaurement definition for mismatch between pull - up and pull - down: mmpupd: measure ron pu and ron pd , both at 0.5 x vddq: mm pu p d = x 100 for example, with mmpupd(max) = 15% and ronpd = 0.85, ronpu must be less than 1.0. 8.2.6.4 output driver temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to the t ables shown b elow . table of output driver sensitivity definition resistor vout min max unit note s ron pd 0.5 x vddq 85 C (dr ondt | t | ) C (dron d v | v | ) 115 + (drondt | t | ) + (drondv | v | ) % 1, 2 ron pu note s : 1. t = t C t (@calibration), v=v C v(@ calibration). 2. drondt and drondv are not subject to production test but are verified by design and characterization. table of output driver temperature and voltage sensitivity symbol parameter m i n max unit note drondt ron temperature sensitivity 0.00 0.75 % / c drondv ron voltage sensitivity 0.00 0.20 % / mv ronnom ronpd ronpu C
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 94 - 8.2.6.5 ron pu and ron pd characteristics without zq calibration output driver impedance ron is defined by design and characterization as default setting . table of output driver dc electrical characteristics with out zq calibration ro n nom resistor vout min nom max unit note 34.3 ron34pd 0.5 x v ddq 24 34.3 44.6 1 ron34pu 0.5 x v ddq 24 34.3 44.6 1 40.0 ron40pd 0.5 x v ddq 28 40 52 1 ron40pu 0.5 x v ddq 28 40 52 1 48.0 ron48pd 0.5 x v ddq 33.6 48 62.4 1 ron48pu 0.5 x v ddq 33.6 48 62.4 1 60.0 ron60pd 0.5 x v ddq 42 60 78 1 ron60pu 0.5 x v ddq 42 60 78 1 80.0 ron80pd 0.5 x v ddq 56 80 104 1 ron80pu 0.5 x v ddq 56 80 104 1 12 0.0 ron 12 0pd 0.5 x v ddq 84 120 156 1 ron 12 0pu 0.5 x v ddq 84 120 156 1 note: across entire operating temperature range, without calibration.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 95 - 8.2.6.6 r zq i - v curve table of rzq i - v curve v ol t ag e [v] ro n = 2 4 0 (rzq) pull - d o w n pull - u p c u rrent [ma ] / ro n [ohms ] current [ ma] / r o n [ o h m s] default value after zqreset with ca l ibrati on default value after zqreset w i th c ali b rat i on m in ma x m in ma x m in ma x m in ma x [ma] [ma] [ma] [ma] [ma] [ma] [ma] [ma] 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.05 0.19 0.32 0.21 0.26 - 0.19 - 0.32 - 0.21 - 0.26 0.10 0.38 0.64 0.40 0.53 - 0.38 - 0.64 - 0.40 - 0.53 0.15 0.56 0.94 0.60 0.78 - 0.56 - 0.94 - 0.60 - 0.78 0.20 0.74 1.26 0.79 1.04 - 0.74 - 1.26 - 0.79 - 1.04 0.25 0.92 1.57 0.98 1.29 - 0.92 - 1.57 - 0.98 - 1.29 0.30 1.08 1.86 1.17 1.53 - 1.08 - 1.86 - 1.17 - 1.53 0.35 1.25 2.17 1.35 1.79 - 1.25 - 2.17 - 1.35 - 1.79 0.40 1.40 2.46 1.52 2.03 - 1.40 - 2.46 - 1.52 - 2.03 0.45 1.54 2.74 1.69 2.26 - 1.54 - 2.74 - 1.69 - 2.26 0.50 1.68 3.02 1.86 2.49 - 1.68 - 3.02 - 1.86 - 2.49 0.55 1.81 3.30 2.02 2.72 - 1.81 - 3.30 - 2.02 - 2.72 0.60 1.92 3.57 2.17 2.94 - 1.92 - 3.57 - 2.17 - 2.94 0.65 2.02 3.83 2.32 3.15 - 2.02 - 3.83 - 2.32 - 3.15 0.70 2.11 4.08 2.46 3.36 - 2.11 - 4.08 - 2.46 - 3.36 0.75 2.19 4.31 2.58 3.55 - 2.19 - 4.31 - 2.58 - 3.55 0.80 2.25 4.54 2.70 3.74 - 2.25 - 4.54 - 2.70 - 3.74 0.85 2.30 4.74 2.81 3.91 - 2.30 - 4.74 - 2.81 - 3.91 0.90 2.34 4.92 2.89 4.05 - 2.34 - 4.92 - 2.89 - 4.05 0.95 2.37 5.08 2.97 4.23 - 2.37 - 5.08 - 2.97 - 4.23 1.00 2.41 5.20 3.04 4.33 - 2.41 - 5.20 - 3.04 - 4.33 1.05 2.43 5.31 3.09 4.44 - 2.43 - 5.31 - 3.09 - 4.44 1.10 2.46 5.41 3.14 4.52 - 2.46 - 5.41 - 3.14 - 4.52 1.15 2.48 5.48 3.19 4.59 - 2.48 - 5.48 - 3.19 - 4.59 1.20 2.50 5.55 3.23 4.65 - 2.50 - 5.55 - 3.23 - 4.65
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 96 - figure of ron = 240 ohms iv curve after zqreset figure of ron = 240 ohms iv curve after c alibration p d m i n p d m a x p u m i n p u m a x 0 - 2 - 4 - 6 2 4 6 m a 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 1 . 2 v o l t a g e p d m i n p d m a x p u m i n p u m a x 0 - 2 - 4 - 6 2 4 6 m a 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 1 . 2 v o l t a g e
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 97 - 8.2.6.7 input/output capacitance table of input/ o utput c apacitance parameter symbol min max units note package input cap ac itance, ck_t and ck_c c pkgck 1 3 pf 1 , 2 package input cap ac itance delta, ck_t and ck_c c dpkgck 0 0.2 pf 1 , 2 , 3 package input cap ac itance, all other input - only pin s c pkgi 1 3 pf 1 , 2 , 4 package input cap ac itance delta, all other input - only pin s c dpkgi - 0. 5 0. 5 pf 1 , 2 , 5 package input /output cap ac itance, dq, dm, dqs_t, dqs_c c pkgi o 1.25 3 .5 pf 1 , 2 , 7 package input /output cap ac itance delta, dqs_t, dqs_c c dpkgdqs 0 0.25 pf 1 , 2 , 6 package input /output cap ac itance delta, dq, dm c dpkgi o - 0.5 0.5 pf 1 , 2 , 7 package input /output cap ac itance, zq pin c pkgzq 0 3 .5 pf 1 , 2 ( t op e r ; v ddq = 1.14 - 1.3v; v ddca = 1.14 - 1.3v; v dd1 = 1.7 - 1.95v, lpddr2 - s4 v dd2 = 1.14 - 1.3v ) . note s : 1. this parameter is not subject to production test. it is verified by design and char ac terization. the cap ac itance is measured ac cording to jep147 (procedure for measuring input cap ac itance using a vector network analyzer (vna) with v dd1 , v dd2 , v ddq , v ss , v ssca , v ssq applied and all other pin s floating. 2. this parameter applies to p ac kage only (does not include die cap ac itance). this value is vendor specific . 3. absolute value of c pkgck _t - c pkgck _c . 4. c pkgi applies to cs_n, cke, ca 0 - ca 9 5. c dpkgi = c pkgi - 0.5 * (c pkgdqs _t + c pkgdqs _c) . 6. absolute value of c pkgdqs _t and c pkgdqs _c. 7. c dpkgio = c pkgio - 0.5 * (c pkgdqs _t + c pkgdqs _c) in byte lane . 8. maximum external load cap ac itance on zq pin, including p ac kaging, board, pin, resistor, and other lpddr2 devices: 5 pf .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 98 - 8.3 i dd specification parameters and test conditions 8.3.1 i dd measurement conditions the following definitions are used within the i dd measurement tables: low: v in v il(dc) max high: v in v ih(dc ) min stable: inputs are stable at a high or low level switching: see tables below . 8.3.1.1 definition of switching for ca input signals switching for ca ck_t (rising) / ck_c (falling) ck_t (falling) / ck_c (rising) ck_t (rising) / ck_c (falling) ck_t (falling) / ck_c (rising) ck_t (rising) / ck_c (falling) ck_t (falling) / ck_c (rising) ck_t (rising) / ck_c (falling) ck_t (falling) / ck_c (rising) cycle n n+1 n+2 n+3 cs_n high high high high ca0 high low low low low high high high ca1 high high high low low low low high ca2 high low low low low high high high ca3 high high high low low low low high ca4 high low low low low high high high ca5 high high high low low low low high ca6 high low low low low high high high ca7 high high high low low low low high ca8 high low low low low high high high ca9 high high high low low low low high note s : 1. cs_n must always be driven high. 2. 50% of ca bus is changing between high and low once per clock for the ca bus. 3. the above pattern (n, n+1, n+2, n+3...) is used continuously during i dd measurement for i dd values that require switching on the ca bus .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 99 - 8.3.1.2 definition of switching for i dd4r clock cke cs_n clock cycle number command ca0 - ca2 ca3 - ca9 all dq rising high low n read_rising hlh lhlhlhl l falling high low n read_falling lll lllllll l rising high high n + 1 nop lll lllllll h falling high high n + 1 nop hlh hlhllhl l rising high low n + 2 read_rising hlh hlhllhl h falling high low n + 2 read_falling lll hhhhhhh h rising high high n + 3 nop lll hhhhhhh h falling high high n + 3 nop hlh lhlhlhl l note s : 1. data strobe (dqs) is changing between high and low every clock cycle. 2. the above pattern (n, n+1...) is used continuously during i dd measurement for i dd4r . 8.3.1.3 definition of switching for i dd4w clock cke cs_n clock cycle number command ca0 - ca2 ca3 - ca9 all dq rising high low n write_rising hll lhlhlhl l falling high low n write_falling lll lllllll l rising high high n + 1 nop lll lllllll h falling high high n + 1 nop hlh hlhllhl l rising high low n + 2 write_rising hll hlhllhl h falling high low n + 2 write_falling lll hhhhhhh h rising high high n + 3 nop lll hhhhhhh h falling high high n + 3 nop hlh lhlhlhl l note s : 1. data strobe (dqs) is changing between high and low every clock cycle. 2. data masking (dm) must always be driven low. 3. the above pattern (n, n+1...) is used continuously during i dd measurement for i dd4w .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 100 - 8.3.2 i dd specifications 8.3.2.1 lpddr2 i dd specification parameters and operating conditio ns, - 40c~ 8 5c (x16, x32) parameter/condition symbol power supply 400 mhz 533 mhz unit note s operating one bank active - precharge current: t ck = t ck(avg)min ; t rc = t rcmin ; cke is high; cs_n is high between valid commands; ca bus inputs are switching; data bus inputs are stable idd0 1 vdd1 10 10 ma 1 idd0 2 vdd2 30 30 ma 1 idd0 in vddca vddq 4.3 4.3 ma 1, 2 idle power - down standby current: t ck = t ck(avg)min ; cke is low; cs_n is high; all banks/rbs idle; ca bus inputs are switching; data bus inputs are stable idd2p 1 vdd1 600 600 a 1 idd2p 2 vdd2 8 00 8 00 a 1 idd2p in vddca vddq 40 40 a 1, 2 idle power - down standby current with clock stop: ck_t =low, ck_c =high; cke is low; cs_n is high; all banks/rbs idle; ca bus inputs are stable; data bus inputs are stable idd2ps 1 vdd1 600 600 a 1 idd2ps 2 vdd2 800 800 a 1 idd2ps in vddca vddq 40 40 a 1 , 2 idle non power - down standby current: t ck = t ck(avg)min ; cke is high; cs_n is high; all banks/rbs idle; ca bus inputs are switching; data bus inputs are stable idd2n 1 vdd1 1 1 ma 1 idd2n 2 vdd2 1 1 4 ma 1 idd2n in vddca vddq 3. 6 3. 6 ma 1 , 2 idle non power - down standby current with clock stop : ck_t =low, ck_c =high; cke is high; cs_n is high; all banks/rbs idle; ca bus inputs are stable; data bus inputs are stable idd2n s 1 vdd1 1 1 ma 1 idd2n s 2 vdd2 9 1 2 ma 1 idd2n s in vddca vddq 3. 6 3. 6 ma 1 , 2 active power - down standby current : t ck = t ck(avg)min ; cke is low; cs_n is high; one bank/ rb active; ca bus inputs are switching; data bus inputs are stable idd3p 1 vdd1 2 2 ma 1 idd3p 2 vdd2 3 3 ma 1 idd3p in vddca vddq 4 5 45 a 1 , 2 active power - down standby current with clock stop: ck_t=low, ck_c=high; cke is low; cs_n is high; one bank/ rb active; ca bus inputs are stable; data bus inputs are stable idd3ps 1 vdd1 2 2 ma 1 idd3ps 2 vdd2 3 3 ma 1 idd3ps in vddca vddq 45 45 a 1 , 2 active non power - down standby current: t ck = t ck(avg)min ; cke is high; cs_n is high; one bank/ rb active; ca bus inputs are switching; data bus inputs are stable idd3n 1 vdd1 2 2 ma 1 idd3n 2 vdd2 1 4 1 8 ma 1 idd3n in vddca vddq 4. 1 4.1 ma 1 , 2 active non power - down standby current with clock stop: ck_t=low, ck_c=high; cke is high; cs_n is high; one bank/ rb active; ca bus inputs are stable; data bus inputs are stable idd3n s 1 vdd1 2 2 ma 1 idd3n s 2 vdd2 1 2 1 6 ma 1 idd3n s in vddca vddq 4.1 4.1 ma 1 , 2
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 101 - parameter/condition symbol power supply 400 mhz 533 mhz unit note s o p e r ati ng b ur s t r e a d c u r r ent: t ck = t ck(avg)min ; cs_ n i s high between valid commands; o n e bank/rb active; bl = 4 ; r l = rlmin; ca b u s i n pu t s a r e s w i t ching; 50 % d a t a c h ang e e ac h burst transfer idd 4r 1 vdd1 4 4 ma 1 idd 4r 2 vdd2 1 6 0 1 9 0 ma 1 idd 4r in vddca 4 4 ma 1 o p e r ati ng b ur s t writ e c ur r e n t: t ck = t ck(avg)min ; cs_ n i s high between valid commands ; o n e bank/rb active; bl = 4 ; w l = w l m i n; ca b u s i n pu t s a r e s w i t ching; 50 % d a t a c h ang e e ac h burst transfer idd 4w 1 vdd1 4 4 ma 1 idd 4w 2 vdd2 200 200 ma 1 idd 4w in vddca vddq 15 15 ma 1 , 2 all bank ref r e s h burst current: t ck = t ck(avg)min ; cke i s high between valid commands ; t rc = t r f c ab min ; burst refresh; ca b u s i n pu t s a r e s w i t ching; da t a bus in p u t s a re s t a b le; idd 5 1 vdd1 38 38 ma 1 idd 5 2 vdd2 120 120 ma 1 idd 5 in vddca vddq 4.1 4.1 ma 1 , 2 all ba n k refre s h a ver a ge c u rr e nt: t ck = t ck(avg)min ; cke i s high between valid commands ; t rc = t r efi ; ca b u s i n pu t s a r e s w i t ching; da t a bus in p u t s a re s t a b le; idd 5ab 1 vdd1 4 4 ma 1 idd 5ab 2 vdd2 14 17 ma 1 idd 5ab in vddca vddq 4.1 4.1 ma 1 , 2 per ba n k refre s h a ver a ge c u rr e nt: t ck = t ck(avg)min ; cke i s high between valid commands ; t rc = t r efi /8 ; ca b u s i n pu t s a r e s w i t ching; da t a bus in p u t s a re s t a b le; idd 5 p b 1 vdd1 3 3 ma 1 idd 5 p b 2 vdd2 13 16 ma 1 idd 5 p b in vddca vddq 4.1 4.1 ma 1 , 2 de e p power - down cu r rent: ck_t=low, ck_c=high; cke is low; ca bus inputs are stable; data bus inputs are stable; idd 8 1 vdd1 15 15 a 1 idd 8 2 vdd2 1 00 1 00 a 1 idd 8 in vddca vddq 40 40 a 1 , 2 note s : 1. i dd values published are the maximum of the distribution of the arithmetic mean . 2. measured currents are the summation of v ddq and v ddca . 3. i dd current specifications are tested after the device is properly initialized .
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 102 - 8.3.2.2 i dd6 partial array self - refresh current , - 40c~ 8 5c (x16, x32) parameter symbol power supply 400 mhz 533 mhz condition unit i dd6 partial array self - refresh current full array idd 6 1 vdd1 90 0 90 0 self refresh current ck_t=low, ck_c=high; cke is low; ca bus inputs are stable; data bus inputs are stable; a idd 6 2 vdd2 200 0 200 0 idd 6 in vddca vddq 40 40 1/2 array idd 6 1 vdd1 80 0 80 0 a idd 6 2 vdd2 1 50 0 1500 idd 6 in vddca vddq 40 40 1/4 array idd 6 1 vdd1 7 00 7 00 a idd 6 2 vdd2 12 00 12 00 idd 6 in vddca vddq 40 40 1/ 8 array idd 6 1 vdd1 650 650 a idd 6 2 vdd2 1000 1000 idd 6 in vddca vddq 40 40 note s : 1. lpddr2 - s 4 sdram uses the same pasr scheme & i dd6 current value categorization as lpddr (jesd209). 2. lpddr2 - s4 sdram de vice s support both bank - masking & segment - masking. the i dd6 currents are measured using bank - masking only . 3. i dd values published are the maximum of the distribution of the arithmetic mean . 8.4 clock specification the jitter specified is a random jitter meeting a gaussian distribution. input clocks violating the min/max values may result in malfunction of the lpddr2 de vice. 8.4.1 definition for t ck(avg) and n ck t ck(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. tck ( avg ) = / n where n = 200 unit t ck(avg) represents the actual clock average t ck(avg) of the input clock under operation. unit n ck represents one clock cycle of the input clock, counting the actual clock edges. t ck(avg) may change by up to 1% within a 100 clock cycle w indow, provided that all jitter and timing specs are met. 8.4.2 definition for t ck(abs) t ck(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. t ck(abs) is not subject to production test. ? ? ? ? ? ? ? ? ? ? n j j tck 1
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 103 - 8.4.3 definition for t ch(avg) and t cl(avg) t ch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses . tch ( avg ) = / ( n tck ( avg )) where n = 200 t cl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. tcl ( avg ) = / ( n tck ( avg )) where n = 200 8.4.4 definition for t jit(per) t jit(per) is the single period jitter defined as the largest deviation of any signal t ck from t ck(avg) . t jit(per) = min/max of {t cki - t ck(avg) where i = 1 to 200}. t jit(per) ,act is the actual clock jitter for a given system. t jit(per) ,allowed is the specified allowed clock period jitter . t jit(per) i s not subject to production test. 8.4.5 definition for t jit(cc) t jit(cc) is defined as the absolute difference in clock period between two consecutive clock cycles. t jit(cc) = max of |{t cki + 1 - t cki }|. t jit(cc) defines the cycle to cycle jitter. t jit(cc) is not subject to production test. 8.4.6 definition for t err(nper) t err(nper) is defined as the cumulative error across n multiple co nsecutive cycles from t ck(avg) . t err(nper) ,act is the actual clock jitter over n cycles for a given system. t err(nper) ,allowed is the specified allowed clock period jitter over n cycles. t err(nper) is not subject to production test. t err ( nper ) = C n tck ( avg ) t err(nper) ,min can be calculated by the formula shown below: t err ( nper ) , min = (1 + 0.68 ln ( n )) t jit ( per ) , min t err(nper) ,max can be calculated by the formula shown below: t err ( nper ) , m ax = (1 + 0.68 ln ( n )) t jit ( per ) , m ax using these equations, t err(nper) tables can be generated for each t jit(per) ,act value. ? ? ? ? ? ? ? ? n j j tch 1 ? ? ? ? ? ? ? ? n j j tcl 1 ? ? ? ? ? ? ? ? ? ? ? ? 1 n i i j j tck
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 104 - 8.4.7 definition for duty d ycle j itter t jit(duty) t jit(duty) is defined with absolute and average specification of t ch / t cl . t jit ( duty ) , min = min (( tch ( abs ), min C tch ( avg ), min ), ( tcl ( abs ), min C tcl ( avg ), min )) x tck ( avg ) tjit ( duty ), m ax = m ax (( tch ( abs ), m ax C tch ( avg ), m ax ), ( tcl ( abs ), m ax C tcl ( avg ), m ax )) x tck ( avg ) 8.4.8 definition for t ck(abs) , t ch(abs ) and t cl(abs) these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at a ll times. table of definition for t ck(abs) , t ch(abs) , and t cl(abs) parameter symbol min unit absolute clock period t ck(abs) t ck(avg),min + t jit(per),min p s absolute clock high pulse width t ch(abs) t ch(avg),min + t jit(duty),min / t ck(avg)min t ck(avg) absolute clock low pulse width t cl(abs) t cl(avg),min + t jit(duty),min / t ck(avg)min t ck(avg) note s : 1. t ck(avg),min is expressed is ps for this table. 2. t jit(duty),min is a negative value. 8.5 period clock jitter lpddr2 devices can tolerate some clock period jitter without core timing parameter de - rating. this section describes device timing requirements in the presence of clock period jitter (t jit(per) ) in excess of the values found in section 8 . 7 .1 lpddr2 ac timing table and how to determine cycle time de - rating and clock cycle de - rating. 8.5.1 clock p eriod j itter e ffects on c ore t iming p arameters (t rcd , t rp , t rtp , t wr , t wra , t wtr , t rc , t ras , t rrd , t faw ) core timing parameters extend across multiple clock cycles. period clock jitter will impact these parameters when measured in numbers of clock cycles. when the device is operated with clock jitter within the specification limits, the lpddr2 device is character ized and verified to support t nparam = ru{t param / t ck(avg )}. when the device is operated with clock jitter outside specification limits, the number of clocks or t ck(avg) may need to be increased based on the values for each core timing parameter. 8.5.1.1 cycle t ime d e - rating for c ore t iming p arameters for a given number of clocks (t nparam ), for each core timing parameter, average clock period (t ck(avg) ) and actual cumulative period error (t err (t nparam ),act) in excess of the allowed cumulative period error (t err ( t nparam ),allowed), the equation below calculates the amount of cycle time de - rating (in ns ) required if the equation results in a positive value for a core timing parameter (t core ). cycletimederating = max a cycle time derating analysis should be conducted for each core timing parameter. the amount of cycle time derating required is the maximum of the cycle time de - ratings determined for each individual core timing parameter. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 , ) ( ), ( ), ( avg tck tnparam allowed tnparam terr act tnparam terr tparam
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 105 - 8.5.1.2 clock cycle d e - rating for c ore t iming p arameters for a given number of clocks (t nparam ) for each core timing parameter, clock cycle de - rating should be specified with amount of period jitter (t jit(per) ). for a given number of clocks (t nparam ), for each core timing parameter, average clock period (t ck(avg) ) and actual cumulative period error (t err (t nparam ),act) in excess of the allowed cumulative period error (t err (t nparam ),allowed), the equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a core timing parameter (t core ). clockcyclederating = ru a clock cycle de - rating analysis should be conducted for each core timing parameter. 8.5.2 clock j itter e ffects on command/address t iming p arameters (t is , t ih , t iscke , t ihcke , t isb , t ihb , t isckeb , t ihcke b ) these parameters are measured from a comma nd/address signal (cke, cs, ca0 - ca9) transition edge to its respective clock signal (ck_t/ck_c) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit( per) , as the setup and hold are relative to the clock signal crossing that latches the command/address. regardless of clock jitter values, these values shall be met. 8.5.3 clock j itter e ffects on read t t iming p arameters 8.5.3.1 t rpre when the device is operated with input clock jitter, t rpre needs to be de - rated by the actual period jitter (t jit(per) ,act,max ) of the input clock in excess of the allowed period jitter (t jit(per ),allowed,max ). output de - ratings are relative to the input clock. trpre ( min, derated ) = for example, if the measured jitter into a lpddr2 - 800 device has t ck(avg) = 2500 ps , t jit(per) ,act,min = - 172 ps and t jit(per) ,act,max = + 193 ps , then t rpre ,min ,derated = 0.9 - (t jit(per),act,max - t jit(per) ,allowed,max )/t ck(avg) = 0.9 - (193 - 100)/2500= .8628 t ck(avg) 8.5.3.2 t lz(dq) , t hz(dq) , t dqsck , t lz(dqs) , t hz(dqs) these parameters are measured from a specific clock edge to a data signal (dmn, dqm.: n=0,1,2,3. m=0 C 31) transition and will be met with respect to that clock edge. therefore, they are not affected by the amount of clock jitter applied (i.e. t jit(per) . 8.5.3.3 t qsh , t qsl these parameters are affected by duty cycle jitter which is represented by t ch(abs)min and t cl(abs)min . t qsh(abs)min = t ch(abs)min C 0.05 t qsl(abs)min = t cl(abs)min C 0.05 these parameters determine absolute data - valid window at the lpddr2 device pin . absolute min data - valid window @ lpddr2 device pin = min { ( t qsh(abs) min * t ck(avg) min C t dqsq max C t qhs max ) , ( t qsl(abs) min * t ck(avg) min C t dqsqmax C t qh smax ) } this minimum data - valid window shall be met at the target frequency regardless of clock jitter. tnparam avg tck allowed tnparam terr act tnparam terr tparam ? ? ? ? ? ? ? ? ? ) ( ), ( ), ( ? ? ? ? ? ? ? ? ? ? ) ( , ), ( , , 9 . 0 avg tck max allowed per tjit max act tjit(per)
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 106 - 8.5.3.4 t rpst t rpst is affected by duty cycle jitter which is represented by t cl(abs) . therefore t rpst(abs)min can be specified by t cl(abs)min . t rpst(abs)min = t cl(abs)min C 0.05 = t qsl(abs)min 8.5.4 clock j itter e ffects on write t iming p arameters 8.5.4.1 t ds, tdh these parameters are measured from a data si gnal (dmn, dqm.: n=0,1,2,3. m=0 C 31) transition edge to its respective data strobe signal (dqsn_t, dqsn_c : n=0,1,2,3) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit(per) , as the setup and hold are relative to the clock signal crossing that latches the command/address. regardless of clock jitter values, these values shall be met. 8.5.4.2 t dss , t dsh these parameters are measured from a data strobe signal (dqsx_t, dqsx_c) crossing to its respective clock signal (ck_t/ck_c) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit(per) , as the setup and hold are relative to the clock signal crossing that latches the command/address. regardless of clock jitter values, these values shall be met. 8.5.4.3 t dqss this parameter is measured from a data strobe signal (dqsx_t, dqsx_c) crossing to the subsequent clock signal (ck_t/ck_c) crossing. when the device is operated with input clock jitter, this parameter needs to be de - rated by the actual period jitter t jit(per),act of the input clock in excess of the allowed period jitter t jit(per),allowed . tdqss ( min, derated ) = tdqss ( max, derated ) = for example, if the measured jitter into a lpddr2 - 800 device has t ck(avg) = 2500 ps , t jit(per),act,min = - 172 ps and t jit(per),act,max = + 193 ps , then t dqss,(min,derated) = 0.75 - (t jit(per),act,min - t jit(per),allowed,min) /t ck(avg) = 0.75 - ( - 172 + 100)/2500 = .7788 t ck(avg) and t dqss,(max,derated) = 1.25 - (t jit(per),act,max - t jit(per),allowed,max) /t ck(avg) = 1.25 - (193 - 100)/2500 = 1.2128 t ck(avg) ) ( , ), ( , ), ( 75 . 0 avg tck min allowed per tjit min act per tjit ? ? ) ( , ), ( , ), ( 25 . 1 avg tck max allowed per tjit max act per tjit ? ?
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 107 - 8.6 refresh requireme nts 8.6.1 refresh requirement parameters parameter symbol 1 gb unit number of banks 8 refresh window t case 85c t refw 32 ms required number of refresh commands (min) r 4 , 096 a verage time between refresh commands (for reference only) t case 85c refab t refi 7 . 8 s ref p b t refi pb 0.975 s refresh cycle time t rfcab 13 0 ns per bank refresh cycle time t rfc p b 60 ns burst refresh window = 4 x 8 x t rfcab t refbw 4 . 16 s
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 108 - 8.7 ac timings 8.7.1 lpddr2 ac timing ( no te 6 apply to the entire table ) parameter symbol min / max min t c k data rate unit 1066 933 800 667 533 400 333 max. frequency *4 ~ 533 466 400 333 266 200 166 mhz clock timing average clock period t ck(avg) min 1.875 2.15 2.5 3 3.75 5 6 ns max 100 average high pulse width t ch(avg) min 0.45 t ck(avg) max 0.55 average low pulse width t cl(avg) min 0.45 t ck(avg) max 0.55 absolute clock period t ck(abs) min t ck(avg)min + t jit(per)min ps absolute clock high pulse width (with allowed jitter) t ch(abs) , allowed min 0.43 t ck(avg) max 0.57 absolute clock low pulse width (with allowed jitter) t cl(abs) , (allowed) min 0.43 t ck(avg) max 0.57 clock period jitter (with allowed jitter) t jit(per) , (allowed) min - 90 - 95 - 100 - 110 - 120 - 140 - 150 ps max 90 95 100 1 1 0 120 140 150 maximum clock jitter between two consecutive clock cycles (with allowed jitter) t jit(cc) , allowed max 180 190 200 220 240 280 300 ps duty cycle jitter (with allowed jitter) t jit(duty), allowed min min ((t ch(abs),min - t ch(avg),min) , (t cl(abs),min - t cl(avg),min) ) * t ck(avg) ps max max ((t ch(abs),max - t ch(avg),max) , (t cl(abs),max - t cl(avg),max) ) * t ck(avg) ps cumulative error across 2 cycles t err(2per) , (allowed) min - 132 - 140 - 14 7 - 1 62 - 1 77 - 206 - 221 ps max 132 140 147 162 177 206 221 cumulative error across 3 cycles t err(3per) , (allowed) min - 157 - 166 - 175 - 192 - 210 - 245 - 262 ps max 157 166 175 192 210 245 262 cumulative error across 4 cycles t err(4per) , (allowed) min - 175 - 185 - 194 - 214 - 233 - 272 - 291 ps max 175 185 194 214 233 272 291 cumulative error across 5 cycles t err(5per) , (allowed) min - 188 - 199 - 209 - 230 - 251 - 293 - 314 ps max 188 199 209 230 251 293 314 cumulative error across 6 cycles t err(6per) , (allowed) min - 200 - 211 - 222 - 244 - 266 - 311 - 333 ps max 200 211 222 244 266 311 333 cumulative error across 7 cycles t err(7per) , (allowed) min - 209 - 221 - 232 - 256 - 279 - 325 - 348 ps max 209 221 232 256 279 325 348 cumulative error across 8 cycles t err(8per) , (allowed) min - 217 - 229 - 241 - 2 6 6 - 290 - 338 - 362 ps max 217 229 241 2 6 6 290 338 362 cumulative error across 9 cycles t err(9per) , (allowed) min - 224 - 237 - 249 - 274 - 299 - 349 - 374 ps max 224 237 249 274 299 349 374 cumulative error across 10 cycles t err(10per) , (allowed) min - 231 - 244 - 257 - 282 - 308 - 359 - 385 ps max 231 244 257 282 308 359 385 cumulative error across 11 cycles t err(11per) , (allowed) min - 237 - 250 - 263 - 289 - 316 - 368 - 395 ps max 237 250 263 289 316 368 395 cumulative error across 12 cycles t err(12per) , (allowed) min - 242 - 256 - 269 - 296 - 323 - 377 - 403 ps max 242 256 269 296 323 377 403 cumulative error across n = 13, 14 . . . 49, 50 cycles t err(nper) , (allowed) min t err(nper),allowed,min = (1 + 0.68ln(n)) * t jit(per),allowed,min ps max t err(nper),allowed,max = (1 + 0.68ln(n)) * t jit(per),allowed,max
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 109 - parameter symbol min / max min t ck data rate unit 1066 933 800 667 533 400 333 zq calibration parameters initialization calibration time t zqinit min 1 s full calibration time t zqcl min 6 360 ns short calibration time t zqcs min 6 90 ns calbration reset time t zqreset min 3 50 ns read parameters *11 dqs output access time from ck_t/ck_c t dqsck min 2500 ps max 5500 dqsck delta short *15 t dqsckds max 330 380 450 540 670 900 1080 ps dqsck delta medium *16 t dqsckdm max 680 780 900 1050 1350 1800 1900 ps dqsck delta long *17 t dqsckdl max 920 1050 1200 1400 1800 2400 - ps dqs - dq skew t dqsq max 200 220 240 280 340 400 500 ps data hold skew factor t qhs max 230 260 280 340 400 480 600 ps dqs output high pulse width t qsh min t ch(abs) - 0.05 t ck(avg) dqs output low pulse width t qsl min t cl(abs) - 0.05 t ck(avg) data half period t qhp min min(t qsh , t qsl ) t ck(avg) dq / dqs output hold time from dqs t qh min t qhp - t qhs ps read preamble *12,*13 t rpre min 0.9 t ck(avg) read postamble *12,*14 t rpst min t cl(abs) - 0.05 t ck(avg) dqs low - z from clock *12 t lz(dqs) min t dqsck(min) - 300 ps dq low - z from clock *12 t lz(dq) min t dqsck(min) - (1.4 * t qhs(max) ) ps dqs high - z from clock *12 t hz(dqs) max t dqsck(max) - 100 ps dq high - z from clock *12 t hz(dq) max t dqsck(max) + (1.4 * t dqsq(max) ) ps write parameters *11 dq and dm input hold time (vref based) t dh min 210 235 270 350 430 480 600 ps dq and dm input setup time (vref based) t ds min 210 235 270 350 430 480 600 ps dq and dm input pulse width t dipw min 0.35 t ck(avg) write command to 1st dqs latching transition t dqss min 0.75 t ck(avg) max 1.25 dqs input high - level width t dqsh min 0.4 t ck(avg) dqs input low - level width t dqsl min 0.4 t ck(avg) dqs falling edge to ck setup time t dss min 0.2 t ck(avg) dqs falling edge hold time from ck t dsh min 0.2 t ck(avg) write postamble t wpst min 0.4 t ck(avg) write preamble t wpre min 0.35 t ck(avg) cke input parameters cke min. pulse width (high and low pulse width) t cke min 3 3 t ck(avg) cke input setup time t iscke *2 min 0.25 t ck(avg) cke input hold time t ih cke *3 min 0.25 t ck(avg)
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 110 - parameter symbol min / max min t ck data rate unit 1066 933 800 667 533 400 333 command address input parameters *11 address and control input setup time (vref based) t is *1 min 220 250 290 370 460 600 740 ps address and control input hold time (vref based) t ih *1 min 220 250 290 370 460 600 740 ps address and control input pulse width t ipw min 0.40 t ck(avg) boot parameters (10 mhz - 55 mhz) *5, 7, 8 clock cycle time t ckb max 1 00 ns min 18 cke input setup time t isckeb min 2 .5 ns cke input hold time t ihckeb min 2 .5 ns address & control input setup time t isb min 1150 ps address & control input hold time t ihb min 1150 ps dqs output data access time from ck_t/ck_c t dqsckb min 2.0 ns max 10.0 data strobe edge to ouput data edge tdqsqb - 1.2 t dqsqb max 1.2 ns data hold skew factor t qhsb max 1.2 ns mode register parameters mode register write command period t mrw min 5 5 t ck(avg) mode register read command period t mrr min 2 2 t ck(avg) lpddr2 sdram core parameters *9 read latency rl min 3 8 7 6 5 4 3 3 t ck(avg) write latency wl min 1 4 4 3 2 2 1 1 t ck(avg) active to active command period t rc min t ras + t rpab (with all - bank precharge) t ras + t rppb (with per - bank precharge) ns cke min. pulse width during self - refresh (low pulse width during self - refresh) t ckesr min 3 15 ns self refresh exit to next valid command delay t xsr min 2 t rfcab + 10 ns exit power down to next valid command delay t xp min 2 7.5 ns cas to cas delay t ccd min 2 2 t ck(avg) internal read to precharge command delay t rtp min 2 7.5 ns ras to cas delay t rcd fast 3 15 ns row precharge time (single bank) t rppb fast 3 15 ns row precharge time (all banks) t rpab 8 - bank fast 3 1 8 ns row active time t ras min 3 42 ns max - 70 s write recovery time t wr min 3 15 ns internal write to read command delay t wtr min 2 7.5 10 ns active bank a to active bank b t rrd min 2 10 ns four bank activate window t faw min 8 50 60 ns minimum deep power down time t dpd min 500 s
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 111 - parameter symbol min / max min t ck data rate unit 1066 933 800 667 533 400 333 lpddr2 temperature de - rating tdqsck de - rating t dqsck (derated) max 5620 6000 ps core timings temperature de - rating t rcd (derated) min t rcd + 1.875 ns t rc (derated) min t rc + 1.875 ns t ras (derated) min t ras + 1.875 ns t rp (derated) min t rp + 1.875 ns t rrd (derated) min t rrd + 1.875 ns note s : 1. input set - up/hold time for signal (ca [ 0 :n] , cs_n). 2. cke input setup time is measured from cke reaching high/low voltage level to ck_t/ck_c crossing. 3. cke input hold time is measured from ck_t/ck_c crossing to cke reaching high/low voltage level . 4. frequency values are for reference only. clock cycle time (t ck ) shall be used to determine device capabilities . 5. to guarantee device operation before the lpddr2 device is configured a number of ac boot timing parameters are defined in this t able. boot parameter symbols have the letter b appended, e.g. t ck during boot is t ckb . 6. frequency values are for reference only. clock cycle time (t ck or t ckb ) shall be used to determine device capabilities. 7. the sdram will se t some mode register default values upon receiving a reset (mrw) command as specified in mode register definition. 8. the output skew parameters are measured with ron default settings into the reference load. 9. the min t ck column applies only when t ck is grea ter than 6 ns for lpddr2 - s 4 devices . 10. all ac timings assume an input slew rate of 1v/ ns . 11. read, write, and input setup and hold values are referenced to vref . 12. for low - to - high and high - to - low transitions, the timing reference will be at the point when the signal crosses v tt . t hz and t lz transitions occur in the same access time (with respect to clock) as valid data transitions. these parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for t r pst , t hz(dqs) and t hz(dq) ), or begins driving (for t rpre , t lz(dqs) , t lz(dq) ). b elow hsul_12 driver output reference load for timing and slew rate figure shows a method to calculate the point when device is no longer driving t hz(dqs) and t hz(dq) , or beg ins driving t lz(dqs ), t lz(dq) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 112 - figure of hsul_12 driver output reference load for timing and slew rate the parameters t lz(dqs) , t lz(dq) , t hz(dqs) , and t hz(dq) are defined as single - ended. the timing parameters t rpre and t rpst are determined from the differential signal dqs_t - dqs_c. 13. measured from the start driving of dqs_t - dqs_c to the start driving the first rising strobe edge. 14. measured from the from start driving the last falling strobe edge to the stop driving dqs_t , dqs_c . 15. t dqsckds is the absolute value of the difference between any two t dqsck measurements ( within a byte lane) within a contiguous sequence of bursts within a 160 ns rolling window. t dqsckds is not tested and is guaranteed by design. temperature drift in the system is < 10c / s . values do not include clock jitter . 16. t dqsckdm is the absolute value of the diff erence between any two t dqsck measurements (within a byte lane) within a 1.6 s rolling window. t dqsckdm is not tested and is guaranteed by design. temperature drift in the system is < 10c/ s . values do not include clock jitter . 17. t dqsckdl is the absolute val ue of the difference between any two t dqsck measurements (within a byte lane) within a 32 ms rolling window. t dqsckdl is not tested and is guaranteed by design. temperature drift in the system is < 10c/ s . values do not include clock jitter. v t t + 2 x y m v v t t + y m v v t t - y m v v t t - 2 x y m v v t t a c t u a l w a v e f o r m t l z ( d q s ) , t l z ( d q ) t h z ( d q s ) , t h z ( d q ) v o h - x m v v o h - 2 x x m v v o l + 2 x x m v v o l + x m v v t t v o h v o l 2 x y 2 x x x t 1 t 2 t 1 t 2 y s t o p d r i v i n g p o i n t = 2 x t 1 C t 2 b e g i n d r i v i n g p o i n t = 2 x t 1 C t 2
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 113 - 8.7.2 ca and cs_n s etup, hold and derating for all input signals (ca and cs_n) the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is(base) and t ih(base) value ( see 8 .7 .2.1 ca and cs_n setup and hold base - values for 1v/ ns table ) to the t is and t ih derating value ( see 8 .7 .2.2 derating v alues lpddr2 t is /t ih - ac / dc b ased ac220 table ) . example: t is (total setup time) = t is(base) + t is . setup (t is ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . setup (t is ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il (ac)max . if the actual signal is always earlier than the nominal slew rate line betwe en shaded v ref(dc) to ac region, use nominal slew rate for derating value ( see 8 .7 .2.4 nominal s lew r ate and t vac for s etup t ime t is for ca and cs_n with r espect to c lock f igure ) . if the actual signal is later than the nominal slew rate line anywhere between shaded v ref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value ( see 8 .7 .2.6 tangent l ine for s etup t ime t is for ca and cs_n with r espect to c lock f igure ) . hold (t ih ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il (dc)max and the first crossing of v ref(dc) . hold (t ih ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih (dc) min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded dc to v ref(dc) region, use nominal slew rate for derating value ( see 8 .7 .2.5 nominal s lew r ate for h old t ime t ih for ca and cs_n with r espect to c lock f igure ) . if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc lev el to v ref(dc) level is used for derating value ( see 8 .7 .2.7 tangent l ine for h old t ime t ih for ca and cs_n with r espect to c lock f igure ) . for a valid transition the input signal has to remain above/below v ih/il(ac) for some time t vac ( see 8 .7 .2.3 required t ime t vac above v ih (ac) {below v il (ac) } for v alid t ransition t able ) . although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in 8 .7 .2.2 derating v alues lpddr2 t is /t ih - ac / dc b ased ac220 table , the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. 8.7.2.1 ca and cs_n setup and hold base - values for 1v/ ns u n it [ ps ] lpddr2 - 1066 lpddr2 - 8 0 0 reference t is(base ) 0 7 0 v ih/l( a c) = v re f(dc) 22 0 mv t ih(base) 9 0 16 0 v ih/l( d c) = v r ef(dc) 13 0 mv note: ac/dc referenced for 1v/ ns ca and cs_n slew rate and 2v/ ns differential ck_t - ck_c slew rate.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 114 - 8.7.2.2 derating v alues lpddr2 t is /t ih - ac / dc b ased ac220 t is , t ih derating in [ ps ] ac/dc based ac 22 0 threshold - > v ih(ac) =v ref(dc) + 22 0mv, v il(ac) =v ref(dc) - 22 0mv dc 13 0 threshold - > v ih(dc) =v ref(dc) + 13 0mv, v il(dc) =v ref(dc) - 13 0mv ca , cs_n slew rate v/ ns ck_t,ck_c differential slew rate 4.0 v/ ns 3.0 v/ ns 2.0 v/ ns 1.8 v/ ns 1.6 v/ ns 1.4 v/ ns 1.2 v/ ns 1.0 v/ ns t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t i h 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.5 74 43 73 43 73 43 89 59 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - - 3 - 5 - 3 - 5 13 11 29 27 45 43 - - - - 0.8 - - - - - 8 - 13 8 3 24 19 40 35 56 55 - - 0.7 - - - - - - 2 - 6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 - 3 26 13 42 33 58 65 0.5 - - - - - - - - - - 4 - 4 20 16 36 48 0.4 - - - - - - - - - - - - - 7 2 17 34 note: cell contents - are defined as not supported . 8.7.2.3 required t ime t vac above v ih(ac) {below v il(ac) } for v alid t ransition slew rate [v/ ns ] t vac @ 22 0mv [ ps ] min max > 2.0 175 - 2.0 170 - 1.5 167 - 1.0 163 - 0.9 162 - 0.8 161 - 0.7 159 - 0.6 155 - 0.5 150 - <0.5 150 -
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 115 - 8.7.2.4 nominal s lew r ate and t vac for s etup t ime t is for ca and cs_n with r espect to c lock c k _ c c k _ t v d d c a v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v r e f t o a c r e g i o n n o m i n a l s l e w r a t e n o m i n a l s l e w r a t e v r e f t o a c r e g i o n t i h t i h t i s t i s t v a c t v a c v s s c a s e t u p s l e w r a t e = v r e f ( d c ) - v i l ( a c ) m a x f a l l i n g s i g n a l t f s e t u p s l e w r a t e = v i h ( a c ) m i n - v r e f ( d c ) r i s i n g s i g n a l t r t f t r
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 116 - 8.7.2.5 nominal s lew r ate for h old t ime t ih for ca and cs_n with r espect to c lock c k _ t c k _ c v d d c a v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x d c t o v r e f r e g i o n n o m i n a l s l e w r a t e n o m i n a l s l e w r a t e d c t o v r e f r e g i o n t i h t i h t i s t i s h o l d s l e w r a t e = v r e f ( d c ) - v i l ( d c ) m a x r i s i n g s i g n a l t r h o l d s l e w r a t e = v i h ( d c ) m i n - v r e f ( d c ) f a l l i n g s i g n a l t f t f t r v s s c a
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 117 - 8.7.2.6 tangent l ine for s etup t ime t is for ca and cs_n with r espect to c lock c k _ c c k _ t v d d c a t i h t i h t i s t i s v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x n o m i n a l l i n e t a n g e n t l i n e t a n g e n t l i n e n o m i n a l l i n e v r e f t o a c r e g i o n v r e f t o a c r e g i o n t r t f t v a c t v a c s e t u p s l e w r a t e = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( a c ) m a x ] f a l l i n g s i g n a l t f s e t u p s l e w r a t e = t a n g e n t l i n e [ v i h ( a c ) m i n - v r e f ( d c ) ] r i s i n g s i g n a l t r v s s c a
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 118 - 8.7.2.7 tangent l ine for h old t ime t ih for ca and cs_n with r espect to c lock c k _ t c k _ c t i h t i h t i s t i s v d d c a v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x d c t o v r e f r e g i o n d c t o v r e f r e g i o n n o m i n a l l i n e n o m i n a l l i n e t a n g e n t l i n e t a n g e n t l i n e t r t f h o l d s l e w r a t e = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( d c ) m a x r i s i n g s i g n a l t r h o l d s l e w r a t e = t a n g e n t l i n e [ v i h ( d c ) m i n - v r e f ( d c ) ] f a l l i n g s i g n a l t f v s s c a
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 119 - 8.7.3 data setup, hold and slew rate derating for all input signals (dq, dm) the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet t ds(base) and t dh(base) value ( see 8 .7 .3.1 data setup and hold base - values t able ) to the t ds and t dh ( see 8 .7 .3.2 derating v alues lpddr2 t ds /t dh - ac / dc b ased ac220 t able ) derating value respectively. example: t ds (total setup time) = t ds (base) + t ds . setup (t ds ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . setup (t ds ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac)ma x ( see 8 .7 .3.4 nominal s lew r ate and t vac for s etup t ime t ds for dq with r espect to s trobe f igure ) . if the actual signal is always earlier than the nominal slew rate l ine between shaded v ref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded v ref(dc) to ac region, the slew rate of a tangent line to the actual signal from t he ac level to dc level is used for derating value ( see 8 .7 .3.6 tangent l ine for s etup t ime t ds for dq with r espect to s trobe f igure ) . hold (t dh ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc) max and the first crossing of v ref(dc) . hold (t dh ) nominal slew rat e for a falling sig 5 nal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref(dc) ( see 8 .7 .3.5 nominal s lew r ate for h old time t dh for dq with r espect to s trobe f igure ) . if the actual signal is always later than the nominal slew rate line between shaded dc level to v ref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc ) level is used for derating value ( see 8 .7 .3.7 tangent l ine for h old t ime t dh for dq with r espect to s trobe f igure ) . for a valid transition the input signal has to remain above/below v ih/il(ac) for some time t vac ( see 8 .7 .3.3 required t ime t vac above v ih (ac) {below v il (ac ) } for v alid t ransition t able ) . although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in 8 .7 .3.2 derating v alues lpddr2 t ds /t dh - ac / dc b ased ac220 t able , the derating values may obtained by linear interpolation. these values are typically not subj ect to production test. they are verified by design and characterization . 8.7.3.1 data setup and hold base - values u n it [ ps ] lpddr2 - 1066 lpddr2 - 8 0 0 reference t ds(bas e) - 1 0 50 v ih/l( a c) = v re f(dc) 22 0 mv t dh(b a s e) 8 0 14 0 v ih/l( d c) = v r ef(dc) 13 0 mv note: ac/dc referenced for 1v/ ns dq,dm slew rate and 2v/ ns differential dqs_t - dqs_c slew rate.
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 120 - 8.7.3.2 derating v alues lpddr2 t ds /t dh - ac / dc b ased ac220 t ds , dh derating in [ ps ] ac/dc based a ac 22 0 threshold - > v ih(ac) = v ref(dc ) + 22 0mv, v il(ac) = v ref(dc) - 22 0mv dc 13 0 threshold - > v ih(dc ) = v ref(dc) + 13 0mv, v il(dc) = v ref(dc) - 13 0mv dq , dm slew rate v/ ns dqs_t, dqs_c differential slew rate 4.0 v/ ns 3.0 v/ ns 2.0 v/ ns 1.8 v/ ns 1.6 v/ ns 1.4 v/ ns 1.2 v/ ns 1.0 v/ ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.5 74 43 73 43 73 43 89 59 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - - 3 - 5 - 3 - 5 13 11 29 27 45 43 - - - - 0.8 - - - - - 8 - 13 8 3 24 19 40 35 56 55 - - 0.7 - - - - - - 2 - 6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 - 3 26 13 42 33 58 65 0.5 - - - - - - - - - - 4 - 4 20 16 36 48 0.4 - - - - - - - - - - - - - 7 2 17 34 note: cell contents - are defined as not supported . 8.7.3.3 required t ime t vac above v ih(ac) {below v il(ac ) } for v alid t ransition slew rate [v/ ns ] t vac @ 22 0mv [ ps ] min max > 2.0 175 - 2.0 170 - 1.5 167 - 1.0 163 - 0.9 162 - 0.8 161 - 0.7 159 - 0.6 155 - 0.5 150 - <0.5 150 -
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 121 - 8.7.3.4 nominal s lew r ate and t vac for s etup t ime t ds for dq with r espect to s trobe d q s _ t d q s _ c t d h t d h t d s t d s v d d q n o m i n a l s l e w r a t e v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s q n o m i n a l s l e w r a t e v r e f t o a c r e g i o n v r e f t o a c r e g i o n t v a c t v a c t r t f s e t u p s l e w r a t e = v r e f ( d c ) - v i l ( a c ) m a x f a l l i n g s i g n a l t f s e t u p s l e w r a t e = v i h ( a c ) m i n - v r e f ( d c ) r i s i n g s i g n a l t r
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 122 - 8.7.3.5 nominal s lew r ate for h old time t dh for dq with r espect to s trobe d q s _ t d q s _ c t d h t d h t d s t d s v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s q v d d q h o l d s l e w r a t e = [ v r e f ( d c ) - v i l ( d c ) m a x r i s i n g s i g n a l t r d c t o v r e f r e g i o n n o m i n a l s l e w r a t e n o m i n a l s l e w r a t e d c t o v r e f r e g i o n h o l d s l e w r a t e = [ v i h ( d c ) m i n - v r e f ( d c ) f a l l i n g s i g n a l t f t f t r
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 123 - 8.7.3.6 tangent l ine for s etup t ime t ds for dq with r espect to s trobe d q s _ c d q s _ t t d h t d h t d s t d s v i h ( a c ) m i n v d d q s e t u p s l e w r a t e = t a n g e n t l i n e [ v i h ( a c ) m i n - v r e f ( d c ) r i s i n g s i g n a l t r t v a c t r t a n g e n t l i n e v r e f t o a c r e g i o n n o m i n a l l i n e v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s q t a n g e n t l i n e n o m i n a l l i n e v r e f t o a c r e g i o n t f t v a c s e t u p s l e w r a t e = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( a c ) m a x ] f a l l i n g s i g n a l t f
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 124 - 8.7.3.7 tangent l ine for h old t ime t dh for dq with r espect to s trobe d q s _ c d q s _ t t d h t d h t d s t d s v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s q t a n g e n t l i n e n o m i n a l l i n e d c t o v r e f r e g i o n t r t f h o l d s l e w r a t e = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( d c ) m a x r i s i n g s i g n a l t r d c t o v r e f r e g i o n t a n g e n t l i n e n o m i n a l l i n e h o l d s l e w r a t e = t a n g e n t l i n e [ v i h ( d c ) m i n - v r e f ( d c ) ] f a l l i n g s i g n a l t f
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 125 - 9. package dimensions p ackage outline vfbga 134 ball (10x11.5 mm 2 , ball pitch: 0.65mm, ? =0.40mm) note: 1. ball land:0.45mm, ball opening:0.35mm, 2. pcb ball land suggested Q 0.35mm
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 126 - p ackage outline w fbga 1 68 ball (1 2 x1 2 mm 2 , ball pitch: 0. 5mm, ? =0. 33 mm) note: 1. ball land:0.38mm, ball opening:0.30mm, pcb ball land suggested Q 0.30mm
W97AH6KB / w97ah2kb publication release date: may 15, 2014 revision: a01 - 001 - 127 - 10. rev i sion history version date page description a 01 - 001 may 15, 2014 all initial formally datashee t important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products coul d result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbo nd for any damages resulting from such improper use or sales.

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